JPS61283118A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the variation in the threshold voltage of MESFET by coating the surface of a compound semiconductor substrate with a film which partly contains the component element of the compound semiconductor of the substrate in the composition before heat treating at high temperature, thereby reducing an internal stress which affects the substrate by the heat treating step. CONSTITUTION:An operating layer 3 is formed in a hole of a silicon nitride film 2 on the surface of a semi-insulating GaAs substrate 1. A heat resistant gate electrode 4 is formed at the center of the operating layer by the combination of an RF sputtering method and a reactive ion etching method. Then, with the electrode 4 and the film 2 as masks ions are implanted in dosage. Then, GaAs is, for example, deposited on the substrate as a position source in AsH3 gas atmosphere by an electron beam depositing method to accumulate a Ga-As compound film 5 which contains the component element of the substrate 1 in approx. 0.3mum of thickness. Then, a heat treatment is executed in a lamp heat treating furnace to form a source region 6 and a drain region 7. Further, a plasma etching is performed in gas such as CCl4 to remove the film 5.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a compound semiconductor device, and particularly to a method for manufacturing a field effect transistor including a step of forming source and drain regions using an ion implantation method. It is.

(Summary of the Invention) The present invention provides a method for manufacturing a compound semiconductor device that includes a step of implanting ions into a compound semiconductor substrate, and a subsequent high-temperature heat treatment step for activating the implanted ions. By including a step of coating the surface of the compound semiconductor substrate with gold, which includes at least a part of the constituent elements of the compound semiconductor serving as the substrate, before the high temperature heat treatment step, the heat treatment step does not affect the semiconductor substrate. The purpose of this invention is to significantly reduce internal stress and suppress fluctuations in the threshold voltage of the MPSFET.

(Prior Art and Problems to be Solved by the Invention) Compound semiconductors have higher mobility than conventional silicon (Si), and have characteristics such as the ability to obtain a substrate with a high speed , development of high-frequency operating elements is progressing. In particular, Schottky barrier field effect transistors (MESFETs) using gallium arsenide (GaAs)
), research on miniaturization is actively progressing with the aim of achieving higher integration.

As an example of a conventional method for manufacturing a compound semiconductor device, a GaAs MESFET will be described below. In order to fabricate a fine MESFET with a gate length of 1 μm or less, a technology that involves ion implantation onto the drain region and high-temperature heat treatment to activate the implanted ions is now essential. For GaAa, this high-temperature heat treatment requires a temperature of about 800° C., and it is a well-known fact that at this high temperature, As, which is more volatile than Ga, is significantly released from the GaAs surface.

This is a common problem that occurs not only in GaAs but also in high-temperature heat treatment for activation of compound semiconductors having different vapor pressures.

To avoid this, for example, a 5iOz film or a 5iOz film formed by chemical vapor deposition on the GaAs surface may be coated with a Si3N film and then subjected to high-temperature heat treatment (hereinafter referred to as the capping method); High temperature heat treatment is applied to arsine (AsH).
A method (hereinafter referred to as a capless method) has been used in which the release of As is suppressed by performing the process in an atmosphere containing 2) or in a state in which it is stacked with another QaAs substrate. However, in the camp method, internal stress occurs during the formation of 5ift, St, and N4, internal stress occurs due to volume change of the interlayer during high-temperature heat treatment, and SiO2, Si, and N.

It is known that internal stress occurs due to the difference in coefficient of thermal expansion between the film and GaAs, and this causes fluctuations in the threshold voltage of the FET. B, M, Aspek (P, M, A
SBECK et al. have reported that the Siviezo effect occurs due to the internal stress generated in the Si3N film.
M, ASBECK, C-P, LEE, AND
MC,F, CHANG+ IEEE Trans,
FJelectron Devices*vol1. E
D-31, No. 10.1377 (1984J)
o On the other hand, in the capless method, the use of highly toxic arsine gas and the difficulty in accurately controlling the As pressure at the interface with other GaAs substrates are obstacles to improving productivity.

(Means for Solving the Problems) An object of the present invention is to provide a method for manufacturing a compound semiconductor device including a new coating method for high-temperature heat treatment that solves the above-mentioned conventional drawbacks.

In order to achieve the above object, the main feature of the present invention is to use a material containing at least a part of the composition of the constituent elements of the compound semiconductor as a film that covers the surface of the compound semiconductor during high-temperature heat treatment.

In the conventional capping method, a protective film for Si-based devices,
Sing is widely used as an insulating film.

When Si, N, or a mixture thereof is used,
The material was different from the compound semiconductor of the substrate.

However, according to the present invention, Ga
Since the entire compound of Ga and A8 is formed using As as the thin film source, the coating film is different from the conventional method in that it is composed of the same element as the substrate.

(Example) FIG. 1 is a sectional view of an element for explaining the present invention in detail. As an example, a GaAs MESFET with a self-aligned gate using a high melting point metal material for the gate electrode is shown.
An outline of the formation process of the f/X' drain region will be given below.

First, a silicon nitride film 2 on the surface of a semi-insulating GaAs substrate 1
The active layer 3 is formed in the opening (Fig. 8).

After that, W and Si were used in the center of the active layer to a thickness of 0.2 μm.
A heat-resistant gate electrode 4e is formed by a combination of RF sputtering method and reactive ion etching method (Figure b).Next, this heat-resistant gate electrode 4 and silicon nitride film 2 are formed.
St Io7 'fr 1501ceV with as a mask
Ions are implanted to a dose of 5Xl0I3crn-'' with an acceleration energy of
The ions are activated by heating them to 800°C, but in this case,
In the conventional process, a cap method was used in which the surface of the substrate was coated with a Sin or S or N4 film. In case of misfire ψ, the coating material used at this time is different from the conventional one. That is, in this example, 5 x 10-
' A Ga-As compound film 5 (!-) with a reflective thickness of 0.3 μm is deposited on the surface of the substrate by electron beam evaporation in an As H, gas atmosphere of Torr (Fig. d). After that, Ar gas is deposited in a lamp heat treatment furnace. During.

A heat treatment is applied at 800 DEG C. for 1 minute to completely form the source region 6 and drain region 7, and further plasma etching is performed in CCt4 gas to remove the Ga--As compound film 5 (see figure e). Thereafter, electrodes, protective films, etc. are formed in the same manner as in the prior art, and the -CGaAg MESFET is completed.

Although the Ga--As compound film 5 is formed by electron beam evaporation here, it is also possible to use RF sputtering using a GaAs e target.

It is also possible to form it by chemical vapor deposition using a gas source containing % Ga and Asf. Also, Ga-As
Although the compound film exhibits a composition containing too much lti Ga using these formation methods, this does not impair the effects of the Ga-As compound film described below.

The Ga, A5 compound film 5 deposited to cover the substrate surface is used as a source/drain layer during activation heat treatment at 800°C, as in the case of the conventional capping method using a conventional Sin, St, or N film. It protects the surface of the GaAs substrate 1, which serves as a region, and prevents the release of M into the heat treatment atmosphere in particular.
This has the effect of maintaining the chemical composition of the As substrate surface. This is because the As concentration gradient at the interface between the GaAs substrate surface and the Ga-As compound film is kept small.
This is because the movement of s at the interface is suppressed. SiQ according to conventional technology.

Or S ia N4 'If! The difference from the case where X'ft: is used is that these conventional films exert internal stress on the GaAa substrate surface, whereas the Ga-As compound film of the present invention does not exert any internal stress on the surface of the GaAa substrate. There is a particular thing. Needless to say, the present Ga-As compound film has a coefficient of thermal expansion almost equal to that of the GaAs substrate. Therefore, fluctuations in the threshold voltage of the MESFET due to internal stress as described above do not occur.
Since the CGa--As compound film has a polycrystalline structure, it can be easily and selectively removed from the di-single-crystal GaAs substrate by plasma etching.

(Effects of the Invention) As explained above, by using a Ga-As compound film as a cap film for heat treatment for high-temperature activation,
The internal stress exerted on the QaAs substrate can be significantly reduced, and M
This has the advantage of suppressing fluctuations in the threshold voltage of the ESFET.

Here, a Ga--As compound film is used for the GaAa substrate, but the composition only needs to include Ga and As'x at a sufficient concentration, and this does not prevent other elements from being added to this film.

Furthermore, although GaAB was taken as an example, it is clear that the present invention is also effective in high-temperature heat treatment of other compound semiconductors that exhibit ionic crystallinity and have a large vapor pressure difference between constituent elements. .

[Brief explanation of the drawing]

FIG. 1 shows a self-φ aligned gate type GaAs MESFET fR fabrication process for explaining the present invention in detail. 1...Semi-insulating GaAa substrate 2...Silicon nitride film 3...Active layer 4...Heat-resistant gate electrode 5... Ga-As compound film 6...Source region 7...Drain region

Claims (3)

[Claims] (1) In a method for manufacturing a compound semiconductor device, which includes a step of implanting ions into a compound semiconductor substrate, and a subsequent high-temperature heat treatment step for activating the implanted ions, the surface of the compound semiconductor substrate is 1. A method for manufacturing a compound semiconductor device, comprising the step of coating the substrate with a film containing at least a part of the constituent elements of the compound semiconductor as a substrate. (2) The step of coating with a film containing at least a part of the composition of the constituent elements of the compound semiconductor is performed by a vapor deposition method or a sputtering method using a solid thin film source having the same composition as the compound semiconductor. Claim 1
A method for manufacturing a compound semiconductor device as described in 1. (3) A patent characterized in that the process of coating a compound semiconductor with a film containing at least part of its composition the constituent elements of the compound semiconductor is carried out by chemical vapor deposition using a gas containing the same element as the compound semiconductor. A method for manufacturing a compound semiconductor device according to claim 1.