JPS61292964A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit dissociation through a high-temperature thermal decomposition CVD method for a compound semiconductor while obtaining a passivation film capable of relaxing thermal stress by a method wherein ions are implanted, a plasma silicon oxynitride film is formed, ions are doped to the silicon oxynitride film and the whole is annealed for activation. CONSTITUTION:A plasma silicon oxynitride film 5 is shaped onto the whole surfaces of the upper sections of a substrate 1 and an electrode 3. The silicon oxynitride film 5 lowers the temperature of a process, and a plasma CVD method is used for inhibiting the dissociation of As. P by phosphine PH3 is doped to the silicon oxynitride film 5. The P-doped silicon oxynitride film 5 is employed as a passivation film for annealing a cap, and the whole is annealed for activation. Source and drain electrodes 6 and 7 are formed through a boring process for a contact and the processes of evaporation, a lift-off, etc.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to compound semiconductor MES (Metal Sem
1-conductor) The present invention relates to a method for manufacturing FETs, and particularly relates to activation annealing techniques for GaAs MESFETs.

[Background technology]

In activation annealing of compound semiconductor MESFET,
A passivation film is used to prevent the dissociation of A8 from GaAs and to prevent heavy metal contamination. This passivation film mainly uses 5ins and 5iaN4. By the way, the 5ift film is made of GaAsM'
ESFIT has a problem in that the external diffusion inhibiting force against GaK is small, and therefore interfacial reactions are likely to occur and good interfacial properties cannot be obtained. In addition, Si and N4 films are
The ability to inhibit external diffusion of Ga is large, and the activation rate is also good.
The passivation film is 810! It is considered to be superior to membranes. However, it is inferior to StO in terms of adhesion, and this is thought to be due to the fact that there are many dangling bonds and many interface states.

In addition, the 51mN4 film by CVD method was formed at high temperature (700mN).
~900℃) and %600℃ or higher is A! There is a problem that the dissociation of I becomes severe. Therefore, a plasma 5taN4 film that can be used at low temperatures is used.

There is a problem that large compressive stress is applied.

Regarding the annealing of GaAa devices.

For example, it is shown in Nikkei Electronics November 88, 1982, pages 118 to 119.

[Purpose of the invention]

The object of the present invention is to obtain A of a compound semiconductor, for example, GaA3.
In addition to suppressing the dissociation of s by high-temperature pyrolysis CVD method,
The present invention provides a technology for manufacturing a passivation film that can alleviate thermal stress.

The above and other objects and novel features of the present invention are:
[Summary of the Invention] Representative inventions disclosed in this specification will be briefly summarized as follows.

That is, a plasma silicon oxynitride film that can be processed at a low temperature is formed, this silicon oxynitride film is doped with P (phosphorus) lt in the case of GaAs, and then 7-nitro is performed for activation. .

Because it is a low-temperature treatment using the plasma CVD method, there is little dissociation of As.
OxNy)

By controlling the y composition ratio, the amount of Ga externally diffused can be controlled. Therefore, an appropriate amount of Ga vacancies are generated to achieve a high activation rate. Furthermore, it is also possible to relax the stress and make it zero by P doping.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

In this embodiment, GaAIB is used as the compound semiconductor. In FIG. 1, reference numeral 1 indicates a GaA3 semi-insulating substrate. A tfN channel layer 2 is formed on this substrate 1 using a photoresist film that has been patterned as required. This N channel layer 2 is formed by implanting silicon ions.

After forming the N channel layer 2, a gate electrode material such as WSi or TiW, which is a high melting point metal, is deposited and selectively etched to form a gate electrode of 3 ft.
Form.

Using this gate electrode 3 as a mask, silicon ions are implanted again to form an N+ implant 4 for ohmic contact.
form. In forming the N+ type region 4, for example, a C technique such as a sidewall formation technique for the gate electrode 3 can be used in order to ensure separation between the source and the gate.

The semiconductor region of the MESFET thus formed,
That is, in performing the activation annealing of the N channel layer 2 and the N+ type regions 4 that will become the source and drain, the following steps are performed in this embodiment.

In FIG. 2, a plasma silicon oxynitride (SioxN) film 5 is formed on the entire upper surface of the substrate 1 and the electrode 3. As shown in FIG. This silicon oxynitride film 5 is produced using a plasma CVD method in order to lower the process temperature and suppress the dissociation of As. For example, S i H4+
N O1 type gas aloy is SIH, +NO, +N Ha
system gas can be used, and the processing temperature is about 300 to 35
It is 0°C. In addition, silicon oxynitride (5i
OxNy) The X, 7 composition ratio of the film 5 is S I H4 + N
It is known that O in the system gas can be controlled by the Not/SiH4 flow rate ratio. for example.

Evert, P. G. T., published in April 1981.
'5olid 5tat by Vande Van
This control technology is disclosed in ``e Tech.''.

Therefore, by controlling the amount of Ga external diffusion,
It is possible to obtain a high activation rate by generating an appropriate amount of Ga vacancies.

Further, the silicon oxynitride film 5 is doped with P using phosphine PHs. This is because although the compressive stress is smaller than that of the plasma 5iaN4, a considerable compressive stress is still applied to the plasma silicon oxynitride film 5, which is alleviated by the doped P. It is also possible to reduce the stress to zero through optimization. In addition, in this example, since P to be doped is group II, GaA
There is also a possibility that the interfacial properties may be improved by filling the vacancy at A8 of s.

Thereafter, activation annealing is performed using the P-doped silicon oxynitride film 5 as a bacsibasilon film for cap annealing.

Furthermore, as shown in Figure 3, the process of drilling holes for contacts,
Source and drain electrodes 6 and 7 are formed through processes such as vapor deposition and lift-off. This electrode metal is, for example, AuGe/
It is a Ni/Au alloy.

〔effect〕

(1) A vacuum film is formed by a plasma CVD method at a low temperature of 300 to 350°C.

Therefore, it is possible to obtain the effect that the dissociation of A3 is small and the interfacial properties can be stabilized.

(2) The amount of outward diffusion of Ga can be optimized by controlling the x+y composition of the plasma silicon oxynitride film as the bacsibasilin film. Therefore, an effect can be obtained in that Sl enters the Ga vacancy and acts as a donor, contributing to an improvement in the activation rate.

(3) M combination of GaAa to badge page phosphorus film! iA
P9 of the same family as g! Since it is doped, thermal stress can be optimized. Therefore, the effect of improving interfacial properties and activation rate can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

The present invention can be used for activation annealing of compound semiconductors, and is particularly suitable for use in KGaAa semiconductor devices.

[Brief explanation of the drawing]

Figures tJX1 to WXs are device cross-sectional views showing the manufacturing process of an embodiment in which the semiconductor device manufacturing method according to the present invention is applied to GaAa MESFBTK. 1... Semi-insulating substrate, 2... N channel layer, 3・・・Ge-) to pole, 4
...NW territory 5...Pudge page 1st layer, 6...
- Source electrode, 7... gate electrode.

Claims (1)

[Claims] 1. Perform ion implantation to form a semiconductor region of MESFET using a compound semiconductor, form a plasma silicon oxynitride film as a passivation film for activation annealing of this semiconductor region, and further perform ion implantation to form a semiconductor region of MESFET using a compound semiconductor. 1. A method of manufacturing a semiconductor device, characterized in that doping is performed to relieve thermal stress in a film, and then the activation annealing is performed.