JPS63181422A - Formation of titanium nitride film - Google Patents
Formation of titanium nitride filmInfo
- Publication number
- JPS63181422A JPS63181422A JP1453787A JP1453787A JPS63181422A JP S63181422 A JPS63181422 A JP S63181422A JP 1453787 A JP1453787 A JP 1453787A JP 1453787 A JP1453787 A JP 1453787A JP S63181422 A JPS63181422 A JP S63181422A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium
- ions
- tin
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 230000015572 biosynthetic process Effects 0.000 title abstract description 7
- 239000010936 titanium Substances 0.000 claims abstract description 30
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 13
- -1 nitrogen ions Chemical class 0.000 claims abstract description 11
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 150000003609 titanium compounds Chemical class 0.000 claims abstract description 6
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910052782 aluminium Inorganic materials 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 26
- 230000001133 acceleration Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract description 2
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 3
- 230000002950 deficient Effects 0.000 abstract 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 abstract 1
- 239000010408 film Substances 0.000 description 55
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004949 mass spectrometry Methods 0.000 description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 description 2
- 150000002830 nitrogen compounds Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 241000251730 Chondrichthyes Species 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路製造プロセス等で用いられる窒
化チタン膜の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming a titanium nitride film used in a semiconductor integrated circuit manufacturing process.
従来の技術
窒化チタン（ＴｉＮ）や硅化チタン（ＴｉＳｉり等のチ
タンを含む薄膜は高密度集積回路の低抵抗ゲート材料、
配線材料等への応用が期待され、研究が進められている
。とりわけＴｉＮ はＡＩｌ等の金属に対して良好な拡
散バリア、エレクトロマイグレーション阻止材料となり
、ＴｉＳｉ工は極めてシート抵抗が低く、拡散層のシー
ト抵抗の低減、配線金属と拡散層間のコンタクト抵抗低
減に役立つものと期待されている。Conventional technology Thin films containing titanium, such as titanium nitride (TiN) and titanium silicide (TiSi), are used as low-resistance gate materials for high-density integrated circuits.
It is expected to be applied to wiring materials, etc., and research is progressing. In particular, TiN is a good diffusion barrier and electromigration prevention material for metals such as Al, and TiSi has an extremely low sheet resistance, which is useful for reducing the sheet resistance of the diffusion layer and the contact resistance between the wiring metal and the diffusion layer. It is expected that
ＴｉＮとＴｉＳｉ の２層構造を用いた従来のシリサ
イド化接合ＭＯ５）ランジスタの形成方法について第４
図ａ−ｅを用いて説明する。まず、周知のＭＯ３型集積
回路プロセスによゆ第４図ａに示すＭＯ３構造をシリコ
ン基板１上に形成する。リンドープしたポリシリコンゲ
ート２はＣＶＤ酸化膜３をマスクとして形成され、その
側壁はスペーサ酸化膜４で覆われている。５はゲート酸
化膜、６はソース及びドレイン領域、７は素子間分離の
だめの酸化膜領域である。次にＴｉ をスパッタ法また
は電子ビーム蒸着法により堆積し、数１００人のＴｉ薄
膜８を形成し、Ａｒ等の不活性ガス中にて１ｏＯｏ℃前
後で熱処理し、シリコン表面の出ているソース・ドレイ
ン拡散領域６でＴｉ とシリコンとを反応させ、シリサ
イド領域９を形成する（第４図ｂ）。次にこの基板をＴ
ｉ のエツチング液（例えばＮＨ４ＯＨ＋２Ｈ２ｏ２＋
Ｈ２０）中で処理すると未反応のＴｉはすべてエツチン
グされ、シリサイド化された領域にのみチタンシリサイ
ドＴｉＳｉ、Ｃ９が残りシリサイド化接合６Ａができる
。スペーサ酸化膜４はポリシリコンゲート２とＴｉ薄膜
８の反応を防止するために設けられている（第４図Ｃ）
。次にＣＶＤ法によりリンガラスとノンドープのガラス
の２層からなるＣＶＤ酸化膜１ｏを堆積し、周知のフォ
トリソグラフィ技術、ドライエッチ技術によりシリサイ
ド化接合９上にコンタクトホール１１を形成する（第４
図ｄ）。続いてＴｉＮ膜１膜上２２膜１３をスパッタに
より蒸着しフォトリングラフィ技術、ドライエツチング
技術により配線領域のみにこれら２層の膜を残す（第４
図ｅ）。通常、シリサイド化接合を形成する場合のソー
スＯドレイン領域６は０．１〜０．２μｍと浅いため、
ＴｉＮ膜１膜上２くことができない。Part 4 on the method of forming a conventional silicided junction MO5) transistor using a two-layer structure of TiN and TiSi.
This will be explained using Figures a to e. First, an MO3 structure shown in FIG. 4a is formed on a silicon substrate 1 according to a well-known MO3 type integrated circuit process. A phosphorous-doped polysilicon gate 2 is formed using a CVD oxide film 3 as a mask, and its sidewalls are covered with a spacer oxide film 4. 5 is a gate oxide film, 6 is a source and drain region, and 7 is an oxide film region for isolation between elements. Next, Ti is deposited by sputtering or electron beam evaporation to form several hundred Ti thin films 8, and heat treated at around 100°C in an inert gas such as Ar to form the source with the exposed silicon surface. Ti and silicon are reacted in the drain diffusion region 6 to form a silicide region 9 (FIG. 4b). Next, connect this board to T
i etching solution (e.g. NH4OH+2H2o2+
When treated in H20), all unreacted Ti is etched away, and titanium silicide TiSi and C9 remain only in the silicided region, forming a silicided junction 6A. Spacer oxide film 4 is provided to prevent reaction between polysilicon gate 2 and Ti thin film 8 (FIG. 4C).
. Next, a CVD oxide film 1o consisting of two layers of phosphorous glass and non-doped glass is deposited by the CVD method, and a contact hole 11 is formed on the silicided junction 9 by well-known photolithography and dry etching techniques (the fourth
Figure d). Next, 22 films 13 are deposited on the TiN film 1 by sputtering, and these two films are left only in the wiring area using photolithography and dry etching techniques (the fourth
Figure e). Normally, the source/drain region 6 when forming a silicided junction is as shallow as 0.1 to 0.2 μm;
The TiN film cannot be coated on top of the TiN film.
Ａ２とＴｉＳｉｘ は３５Ｃ）Ｃ程度以上で簡単に反応
してしまうため、４００℃を超える八２ シンタ一時に
Ａ２が接合を越えてシリコン基板１中に拡散し、いわゆ
るＡ２スパイクを生じて大きな接合リークを生じるから
である。Since A2 and TiSix easily react at temperatures above about 35C), when the temperature exceeds 400C, A2 diffuses across the junction and into the silicon substrate 1, causing a so-called A2 spike and causing a large junction leak. This is because it causes
発明が解決しようとする問題点
こうして形成されたＴｉＮ１２をバリア層とする構造は
ＡＩｌスパイクを生じない安定なコンタクトとなるが、
他方製造プロセス上では次の様な問題があることが明ら
かとなってきた。Problems to be Solved by the Invention Although the structure formed in this way using TiN12 as a barrier layer becomes a stable contact that does not cause AIl spikes,
On the other hand, it has become clear that there are the following problems in the manufacturing process.
■ ＴｉＮ膜には適切な反応性ドライエツチングのでき
るガスが現在のところ逐ぐ、フォトレジストや他の材料
との選択比の小さいいわゆるスパッタ性の強いエツチン
グを行なわざるを得ない。このため、エツチング中にパ
ターンシフトを生じ、また残渣のために配線間の短絡を
生じたり、長時間イオンでたたかれるためにデバイス中
に損傷を残したりすることがある。このため微細なパタ
ーンの形成が難しい。(2) At present, there is no gas available for suitable reactive dry etching for the TiN film, so etching with strong sputtering properties, which has a low selectivity with respect to photoresist and other materials, must be performed. This can cause pattern shifts during etching, short circuits between interconnects due to the residue, and damage left in the device due to being bombarded with ions for a long period of time. This makes it difficult to form fine patterns.
■ スパッタ法でＴｉＮ１２を形成する場合、コンタク
トホール１１が微細かつ垂直になるとその底面にＴＬＮ
が付着しにくく々す、バリア層としての信頼性に欠ける
。■ When forming TiN12 by sputtering, if the contact hole 11 is fine and vertical, TLN is formed on the bottom surface.
is difficult to adhere to, and lacks reliability as a barrier layer.
■ ＴｉＮ膜はスパッタ法以外にもＴｉを含む膜を熱窒
化することにより形成できるが、そのためには１０００
℃以上の熱処理が必要でその間不納物プロファイルの変
化等の望ましくない現象を生じる。■ A TiN film can be formed by thermal nitriding of a film containing Ti in addition to the sputtering method;
℃ or higher heat treatment is required, during which undesirable phenomena such as changes in the profile of undeliverables occur.
本発明はこの様な従来のバリア層形成方法の問題点に鑑
みてなされたもので、微細なコンタクトホールにも信頼
性の良いバリア層を比較的低温下で形成する方法を提供
しようとするものである。The present invention was made in view of the problems of the conventional barrier layer forming method, and aims to provide a method for forming a highly reliable barrier layer even in minute contact holes at a relatively low temperature. It is.
また本発明の他の目的は、Ｔ ｉ Ｎ／ｌ’１．の２層
構造を用いてへ２配線のエレクトロマイグレーション現
象発生を抑制する際に、Ｔ ｉ Ｎ／１１１．配線の微
細パターン形成を容易にしようとするものである。Another object of the present invention is to reduce T i N/l'1. When suppressing the electromigration phenomenon of the H2 wiring using the two-layer structure of T i N/111. The purpose is to facilitate the formation of fine wiring patterns.
Ａ４配線のエレクトロマイグレーション発生を抑制する
ために、へ２配線上にＴｉＮ 膜を形成することが効
果的であるが、他方微細配線には余り適用されていなか
った。なぜならば先にも触れた様にＴｉＮ はドライエ
ツチングが難しくエツチング中にパターンシフトを生じ
、微細パターン形成が困難であったからである。In order to suppress the electromigration of A4 wiring, it is effective to form a TiN film on the A4 wiring, but this has not been applied to fine wiring. This is because, as mentioned above, dry etching of TiN is difficult and pattern shift occurs during etching, making it difficult to form fine patterns.
本発明はこの様なエレクトロマイグレーション抑制のた
めのＴｉＮ／Ａｆｆ ２層構造を微細配線に適用可能
にする方法を提供しようとするものである。The present invention aims to provide a method that makes the TiN/Aff two-layer structure for suppressing electromigration applicable to fine wiring.
問題点を解決するだめの手段
上記の様な問題点を解決するために本発明は、ＴｉＮ膜
を形成する工程にイオン打込み法を適用する。すなわち
あらかじめチタン膜またはチタン化合物膜を堆積してお
き、これに窒素イオンまたは窒素を含む化合物イオンを
イオン打込みすることにより、ＴｉＮ膜を形成しようと
するものである。Means for Solving the Problems In order to solve the above problems, the present invention applies an ion implantation method to the process of forming a TiN film. That is, a TiN film is formed by depositing a titanium film or a titanium compound film in advance and implanting nitrogen ions or nitrogen-containing compound ions into the film.
作 用
ＴｉＮ膜が必要とされる殆んどの場合はせいぜい１１０
０ｎから２００ｎｍ程度迄の極く薄いＴｉＮ 膜で充分
である。このためチタン膜またはチタン化合物膜に数Ｋ
ｅＶ から数１０ＫｅＶの加速エネルギーで窒素または
窒素化合物をイオン打込みする事によりこの程度の厚み
のＴｉＮ 膜を形成できる。この際、イオン打込みは
通常の半導体装置の製造工程で使用される様な質量分析
を必ずしも必要としない。イオンの純度に対する要求が
ＴｉＮ 膜を必要としている工程ではかなしゆるやかだ
からである。In most cases where a working TiN film is required, it is no more than 110
An extremely thin TiN film with a thickness of about 0 nm to about 200 nm is sufficient. For this reason, the titanium film or titanium compound film has several K
A TiN film of this thickness can be formed by ion-implanting nitrogen or a nitrogen compound at an acceleration energy of eV to several tens of KeV. At this time, ion implantation does not necessarily require mass spectrometry as used in normal semiconductor device manufacturing processes. This is because the requirements for ion purity are very lenient in processes that require TiN films.
あらかじめチタン膜あるいはチタン化合物膜を、必要と
する微細パターンに加工しておき、次に窒素原子まだは
窒素化合物を基板全体にイオン打込みすることにより上
層がＴｉＮ 層となった微細なパターンを得ることが
できる。あるいはチタン膜あるいはチタン化合物上のＴ
ｉＮ 膜を形成したい部分のみを開口し、他の領域を
イオン打込み阻止材料でマスクしてイオン打込みするこ
とにより部分的にＴｉＮ膜を形成しようとするのが本発
明の方法である。A titanium film or a titanium compound film is processed in advance into the required fine pattern, and then nitrogen atoms or nitrogen compounds are ion-implanted into the entire substrate to obtain a fine pattern with the upper layer being a TiN layer. Can be done. Or T on titanium film or titanium compound
The method of the present invention attempts to partially form a TiN film by opening only the portion where the iN film is desired to be formed and implanting ions while masking the other regions with an ion implantation blocking material.
実施例 本発明について実施例を用いて詳細に説明する。Example The present invention will be explained in detail using examples.
第１図ａから第１図すは本発明をシリサイド化接合ＭＯ
８集積回路に適用した例である。シリサイド化接合形成
を経てコンタクトホール１１形成までの工程（第１図ａ
−ｃ）までは従来例と同様である。コンタクトホールの
底部のチタンシリサイドＴｉＳｉ工９は０．１〜０．２
μと薄い。この一部をＴｉＮ 化するために、第１図ｄ
に示す様に窒素イオ７（Ｎ”）を１〜４０ ＫｅＶ 、
５Ｘ１０１６／ｃＭ −５Ｘ１０１７／ｉの範囲でイオ
ン打込みした。ドーズ量はチタンの原子密度とほぼ同等
になる様に選んだ。イオン打込みはビーム電流を犬とす
るため、質量分析は行なわれなかった。この場合、イオ
ンソースでは窒素ガスを用いているため、イオン流には
窒素イオンのみならず、窒素分子も含まれる。Figure 1a to Figure 1 show the present invention in a silicided junction MO.
This is an example applied to 8 integrated circuits. The process from forming a silicided junction to forming a contact hole 11 (Fig. 1a)
-c) is the same as the conventional example. The titanium silicide TiSi coating 9 at the bottom of the contact hole is 0.1 to 0.2
μ and thin. In order to convert this part into TiN,
As shown in the figure, nitrogen ion 7 (N”) is heated at 1 to 40 KeV,
Ion implantation was performed in the range of 5X1016/cM - 5X1017/i. The dose was selected to be approximately equal to the atomic density of titanium. Mass spectrometry was not performed because the ion implantation uses a constant beam current. In this case, since the ion source uses nitrogen gas, the ion flow includes not only nitrogen ions but also nitrogen molecules.
イオン打込み後、Ａｒ中にて７００℃数分間のラピッド
サーマルアニールを行ない、イオン打込みによるシリサ
イド化接合中の損傷を回復し、同時にＴｉＮ膜１２Ａの
低抵抗化を図った。After the ion implantation, rapid thermal annealing was performed in Ar at 700° C. for several minutes to recover damage in the silicided junction caused by the ion implantation, and at the same time to lower the resistance of the TiN film 12A.
この後、第１図ｅに示す様にＡｎ配線１３を形成し、シ
リサイド化接合を有するＭＯＳトランジスタができあが
る。この様にイオン打込み法によりＴｉＮバリアメタル
を形成することにより、従来プロセスで生じたようなコ
ンタクトホールでのＴｉＮ膜の堆積不良や微細配線形成
の際の不良は生シナイ。ＴｉＮ 膜１２Ａはコンタクト
ホール１１の開口部にのみ自己整合で形成されるため、
歩留りが良い。Thereafter, an An wiring 13 is formed as shown in FIG. 1e, and a MOS transistor having a silicided junction is completed. By forming the TiN barrier metal using the ion implantation method in this way, defects in TiN film deposition in contact holes and defects in fine wiring formation that occur in conventional processes can be avoided. Since the TiN film 12A is formed in a self-aligned manner only at the opening of the contact hole 11,
Good yield.
本実施例ではチタンシリサイド領域９を形成して後にイ
オン打込みを行なったが、順を逆にすることもできる。In this embodiment, titanium silicide region 9 is formed and then ion implantation is performed, but the order can also be reversed.
すなわち第１図ａの工程の後第２図に示す様に、Ｔｉ薄
膜８を全面ば蒸着し、ＴｉＮを形成したい部分のみを開
口するマスクでフォトレジスト１４のパターン出しを行
なう。このフォトレジストをマスクとして窒素イオン打
込みを行ない、所望の領域にのみＴｉＮ１２Ｂを形成す
ることができる。この場合にはＴｉ薄膜８Ａの厚みを決
める際、ＴｉＮ１２Ｂに変質する分を考慮し少し厚くし
て、後工程のシリサイド接合形成にそなえる必要がある
。以下の工程は従来例と同様に取扱うことができる。That is, after the step shown in FIG. 1A, as shown in FIG. 2, a Ti thin film 8 is deposited over the entire surface, and the photoresist 14 is patterned using a mask that opens only the portion where TiN is to be formed. Nitrogen ions are implanted using this photoresist as a mask, and TiN 12B can be formed only in desired regions. In this case, when determining the thickness of the Ti thin film 8A, it is necessary to make it a little thicker in consideration of the change in quality to TiN 12B in order to prepare for the formation of a silicide bond in the later step. The following steps can be handled in the same manner as in the conventional example.
第３図ａ、ｂは本発明を配線のエレクトロマイグレーシ
ョン抑制に適用した第２の実施例を示している。まず、
第３図ａに示す様にシリコン基板１上に形成されたフィ
ールド酸化膜１６上にＡＱ膜、チタン膜をスパッタ法に
よりそれぞれ〜６００ｎｍ、〜５０ｎｍ形成し、公知の
フォトリソグラフィー技術によりフォトレジスト（図示
せず）でパターン出しする。このフォトレジストをマス
クとして塩素及び四塩化硅素を主体とするガス系でプラ
ズマエツチングを行なう。酸素プラズマ等を用いてフォ
トレジストを除去し、微細パターンのＡ２配線１６、チ
タン膜１７が得られる。次に加速エネルギー数ＫｅＶか
ら数１０ＫｅＶで窒素イオン流をシリコン基板全面に照
射する。ドーズ量はチタンの原子密度とほぼ同等になる
様６×１ｏ 〜５ｘ１ｏ ／ｃｎｉ とした（第３図
ｂ）。これによりチタン膜１７は窒化し、ＴｉＮ膜１日
となる。この方法によれば、あらかじめパターンはチタ
ン膜１７、Ａｎ配線１６形成時点で確定しているため、
従来法で問題となったＴｉＮ エツチング時のパター
ンシフト等の問題は生じない。ＴｉＮ膜／Ａｆ！、膜の
２層構造とすることで、Ａｌｌ膜層層際に比べるとヒル
ロックの発生が極めて少なくなり、エレクトロマイグレ
ーションも発生しにくくなることは言うまでもない。こ
の実施例ではＡ２膜１６上にチタン膜１７を形成すると
したが、チタン膜１７の代りにチタンシリサイド膜を用
いても何らさしつかえない。FIGS. 3a and 3b show a second embodiment in which the present invention is applied to suppress electromigration of wiring. first,
As shown in FIG. 3a, an AQ film and a titanium film of ~600 nm and ~50 nm, respectively, are formed on the field oxide film 16 formed on the silicon substrate 1 by sputtering, and a photoresist (Fig. (not shown) to generate a pattern. Using this photoresist as a mask, plasma etching is performed using a gas system mainly containing chlorine and silicon tetrachloride. The photoresist is removed using oxygen plasma or the like to obtain fine patterns of A2 wiring 16 and titanium film 17. Next, the entire surface of the silicon substrate is irradiated with a flow of nitrogen ions at an acceleration energy of several KeV to several tens of KeV. The dose was set to 6×1o to 5×1o/cni so as to be approximately equal to the atomic density of titanium (FIG. 3b). As a result, the titanium film 17 is nitrided and becomes a TiN film for one day. According to this method, since the pattern is determined in advance at the time of forming the titanium film 17 and the An wiring 16,
Problems such as pattern shift during TiN etching, which were problems in the conventional method, do not occur. TiN film/Af! It goes without saying that by having a two-layer structure of the film, hillocks are extremely less likely to occur and electromigration is also less likely to occur compared to when the Al film is layered. In this embodiment, the titanium film 17 is formed on the A2 film 16, but a titanium silicide film may be used instead of the titanium film 17.
発明の効果
この様に本発明を適用することによりサブミクロンルー
ルでの■ コンタクトバリアメタルの形成、■ 金属配
線のエレクトロマイグレーション抑止膜の形成、を高歩
留りで信頼性よく行うことができる。Effects of the Invention As described above, by applying the present invention, (1) formation of a contact barrier metal and (2) formation of an electromigration inhibiting film for metal wiring can be performed with high yield and reliability under the submicron rule.
第１図ａ、ｂ、ｃ、ｄ、ｅは本発明の一実施例を説明す
るだめの工程断面図、第２図は本発明の他の実施例を示
す断面図、第３図ａ、ｂは本発明のさらに他の実施例を
説明するための工程断面図、第４図ａ、ｂ、ｃ、ｄ、ｅ
は従来例を説明するための工程断面図である。
１・・・・・・シリコン基板、８，８Ａ・・・・・・チ
タン薄膜、９・・・・・・シリサイド領域、１２Ａ、１
２Ｂ・・・・・・ＴｉＮ。
１３．１６・・・・・・Ａ２配線、１７・・・・・・チ
タン膜、１８・・・・・・ＴｉＮ膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名！−
シリコン基板
２−、ｌ？リシリコンゲート
３−ＣＶＤ酸イと、膜
ｌ −シリコン墓叔
Ｉ５−酸化膜
１６− パノ 配 祿
１’ｌ −＋ ダ ン 膜
１Ｂ−ＴｉＮＭ
第３図
１− ンリコン＠扱
２− ポリシリコンケート
３−ＣＶＤ酸イ乙バ寓
４− スペーサ鮫化膜
ｇ−ソリサイト化併合Figures 1 a, b, c, d, and e are process sectional views for explaining one embodiment of the present invention, Figure 2 is a sectional view showing another embodiment of the present invention, and Figures 3 a, b 4a, b, c, d, e are process sectional views for explaining still other embodiments of the present invention.
1 is a process sectional view for explaining a conventional example. 1...Silicon substrate, 8,8A...Titanium thin film, 9...Silicide region, 12A, 1
2B...TiN. 13.16...A2 wiring, 17...Titanium film, 18...TiN film. Name of agent: Patent attorney Toshio Nakao and 1 other person! −
Silicon substrate 2-, l? Polysilicon gate 3 - CVD acid and film 1 - Silicon layer I5 - Oxide film 16 - Pano layer 1'l - + Dan film 1B - TiNM Figure 3 1 - Silicon layer 2 - Polysilicon gate 3 -CVD acid evaporation 4- Spacer shark membrane g- Soricytization merging
Claims (7)
ンまたは窒素原子を含むイオンをイオン打込みしてなる
窒化チタン膜の形成方法。(1) A method for forming a titanium nitride film by implanting nitrogen ions or ions containing nitrogen atoms into a titanium film or a film containing a titanium compound.
る様にドーズ量、加速エネルギーを設定してイオン打込
みする特許請求の範囲第１項に記載の窒化チタン膜の形
成方法。(2) The method for forming a titanium nitride film according to claim 1, in which ions are implanted by setting the dose and acceleration energy to be approximately the same as the titanium atomic density contained in the film.
項に記載の窒化チタン膜の形成方法。(3) Claim 1 in which the film is titanium silicide
The method for forming a titanium nitride film described in .
請求の範囲第１項に記載の窒化チタン膜の形成方法。(4) The method for forming a titanium nitride film according to claim 1, wherein the film constitutes a titanium silicided junction.
ニウムを主体とする膜とを含む多層構造膜である特許請
求の範囲第１項に記載の窒化チタン膜の形成方法。(5) The method for forming a titanium nitride film according to claim 1, wherein the film is a multilayer structure film including a titanium film or a titanium silicide film and a film mainly composed of aluminum.
る特許請求の範囲第１項に記載の窒化チタン膜の形成方
法。(6) The method for forming a titanium nitride film according to claim 1, wherein nitrogen ions are implanted after patterning the film.
て前記膜にイオン打込みする特許請求の範囲第１項に記
載の窒化チタン膜の形成方法。(7) The method for forming a titanium nitride film according to claim 1, wherein a mask is formed on the film and ions are implanted into the film through the mask opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1453787A JPS63181422A (en) | 1987-01-23 | 1987-01-23 | Formation of titanium nitride film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1453787A JPS63181422A (en) | 1987-01-23 | 1987-01-23 | Formation of titanium nitride film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181422A true JPS63181422A (en) | 1988-07-26 |
Family
ID=11863899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1453787A Pending JPS63181422A (en) | 1987-01-23 | 1987-01-23 | Formation of titanium nitride film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181422A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5221853A (en) * | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
| JPH0653168A (en) * | 1992-06-05 | 1994-02-25 | Hyundai Electron Ind Co Ltd | Manufacture of titanium silicide contact |
| US5491365A (en) * | 1991-07-12 | 1996-02-13 | Hughes Aircraft Company | Self-aligned ion implanted transition metal contact diffusion barrier apparatus |
| US5494860A (en) * | 1995-03-14 | 1996-02-27 | International Business Machines Corporation | Two step annealing process for decreasing contact resistance |
| US5508212A (en) * | 1995-04-27 | 1996-04-16 | Taiwan Semiconductor Manufacturing Co. | Salicide process for a MOS semiconductor device using nitrogen implant of titanium |
| US5656546A (en) * | 1995-08-28 | 1997-08-12 | Taiwan Semiconductor Manufacturing Company Ltd | Self-aligned tin formation by N2+ implantation during two-step annealing Ti-salicidation |
| US5874351A (en) * | 1996-06-13 | 1999-02-23 | Micron Tecnology, Inc. | Sputtered metal silicide film stress control by grain boundary stuffing |
| US6027990A (en) * | 1996-07-08 | 2000-02-22 | Micron Technology, Inc. | Using implants to lower anneal temperatures |
-
1987
- 1987-01-23 JP JP1453787A patent/JPS63181422A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5221853A (en) * | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
| US5491365A (en) * | 1991-07-12 | 1996-02-13 | Hughes Aircraft Company | Self-aligned ion implanted transition metal contact diffusion barrier apparatus |
| JPH0653168A (en) * | 1992-06-05 | 1994-02-25 | Hyundai Electron Ind Co Ltd | Manufacture of titanium silicide contact |
| US5494860A (en) * | 1995-03-14 | 1996-02-27 | International Business Machines Corporation | Two step annealing process for decreasing contact resistance |
| US5508212A (en) * | 1995-04-27 | 1996-04-16 | Taiwan Semiconductor Manufacturing Co. | Salicide process for a MOS semiconductor device using nitrogen implant of titanium |
| US5656546A (en) * | 1995-08-28 | 1997-08-12 | Taiwan Semiconductor Manufacturing Company Ltd | Self-aligned tin formation by N2+ implantation during two-step annealing Ti-salicidation |
| US5874351A (en) * | 1996-06-13 | 1999-02-23 | Micron Tecnology, Inc. | Sputtered metal silicide film stress control by grain boundary stuffing |
| US6054744A (en) * | 1996-06-13 | 2000-04-25 | Micron Technology Inc. | Metal silicide film stress control by grain boundary stuffing |
| US6204173B1 (en) | 1996-06-13 | 2001-03-20 | Micron Technology, Inc. | Multiple implantation and grain growth method |
| US6027990A (en) * | 1996-07-08 | 2000-02-22 | Micron Technology, Inc. | Using implants to lower anneal temperatures |
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