KR100265228B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR100265228B1 KR100265228B1 KR1019980019182A KR19980019182A KR100265228B1 KR 100265228 B1 KR100265228 B1 KR 100265228B1 KR 1019980019182 A KR1019980019182 A KR 1019980019182A KR 19980019182 A KR19980019182 A KR 19980019182A KR 100265228 B1 KR100265228 B1 KR 100265228B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- silicide layer
- semiconductor device
- layer
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000005468 ion implantation Methods 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 15
- 239000010937 tungsten Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011261 inert gas Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052786 argon Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- -1 spacer ion Chemical class 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 23
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 238000000059 patterning Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 16
- 230000007847 structural defect Effects 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 239000002244 precipitate Substances 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트가 금속 폴리사이드 구조로 형성되고, 접합부가 엘디디(LDD) 구조로 형성되는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a gate is formed of a metal polyside structure and a junction portion is formed of an LED (LDD) structure.
폴리실리콘층 및 금속 실리사이드층의 적층 구조로 이루어지는 금속 폴리사이드 구조는 반도체 소자의 고집적화에 따른 속도 개선의 측면에서 종래의 폴리실리콘을 대체하여 사용되고 있다. 특히 금속 실리사이드층은 텅스텐(W) 및 타이타늄(Ti) 등의 금속을 사용한다. 일반적으로 많이 사용되는 텅스텐 실리사이드(WSix)의 경우 실리콘 조성비를 2 이상, 바람직하게는 2 ∼ 2.8 정도가 되도록 하여 후속 산화 공정시 산화(oxidation) 특성을 개선하면서 하부의 폴리실리콘층과의 접착 강도를 증대시키고 있다.The metal polyside structure, which is a laminated structure of a polysilicon layer and a metal silicide layer, has been used in place of the conventional polysilicon in view of speed improvement due to high integration of semiconductor devices. In particular, the metal silicide layer uses a metal such as tungsten (W) and titanium (Ti). In general, tungsten silicide (WSix), which is commonly used, has a silicon composition ratio of 2 or more, preferably 2 to 2.8, thereby improving the oxidation characteristics during the subsequent oxidation process while improving the adhesive strength with the lower polysilicon layer. It is increasing.
도 1(a) 및 도 1(b)는 종래의 방법에 의한 반도체 소자의 제조 방법을 설명하기 위한 단면도이다.1 (a) and 1 (b) are cross-sectional views for explaining a method for manufacturing a semiconductor device by a conventional method.
도 1(a)에 도시된 것과 같이, 반도체 기판(11) 상에 게이트 산화막(12), 폴리실리콘층(13) 및 텅스텐 실리사이드층(14)을 순차적으로 형성한 후 패터닝하여, 폴리실리콘층(13)과 텅스텐 실리사이드층(14)이 적층된 텅스텐 폴리사이드 게이트(15)가 형성된다. 텅스텐 실리사이드층(14)은 위에서 설명한 바와 같이, 열적 안정성 및 하부 폴리실리콘층(13)과의 접착 강도 증가를 위하여, 실리콘의 조성비를 2 이상으로 제어하여 형성한다.As shown in FIG. 1A, the gate oxide film 12, the polysilicon layer 13, and the tungsten silicide layer 14 are sequentially formed on the semiconductor substrate 11 and then patterned to form a polysilicon layer ( A tungsten polyside gate 15 in which 13) and a tungsten silicide layer 14 is stacked is formed. As described above, the tungsten silicide layer 14 is formed by controlling the composition ratio of silicon to 2 or more in order to increase thermal stability and adhesion strength with the lower polysilicon layer 13.
도 1(b)에 도시된 것과 같이, 반도체 기판(11) 상에 저농도 이온주입 공정으로 저농도 이온주입 영역(16)을 형성하고, 텅스텐 폴리사이드 게이트(15)의 측벽에 스페이서 산화막(17)을 형성한 후, 다시 반도체 기판(11) 상에 고농도 이온주입 공정으로 고농도 이온주입 영역(19)을 형성하여 저농도 및 고농도 이온주입 영역(16 및 19)으로 된 엘디디 구조의 접합부가 형성된다.As shown in FIG. 1B, a low concentration ion implantation region 16 is formed on the semiconductor substrate 11 by a low concentration ion implantation process, and a spacer oxide film 17 is formed on the sidewall of the tungsten polyside gate 15. After the formation, the high concentration ion implantation region 19 is formed on the semiconductor substrate 11 by a high concentration ion implantation process to form a junction of the LED structure having the low concentration and the high concentration ion implantation regions 16 and 19.
상기에서 실리콘의 조성비가 2 이상으로 형성된 텅스텐 실리사이드층(14)은 이러한 과도한 실리콘 성분이 원인이 되어 게이트 패터닝 공정 후에 실시되는 열 공정을 거치는 동안에 도 1(b)에 도시된 것과 같이, 폴리실리콘층(13)과 텅스텐 실리사이드층(14)의 계면 및 텅스텐 실리사이드층(14)의 측벽 쪽에 실리콘 성분이 편석 결정화되어 실리콘 석출물(18)이 형성된다. 이와 같이 텅스텐 실리사이드층(14)이 비정상적으로 변형되므로 인하여 후속 공정으로 형성되는 스페이서 산화막(17)도 역시 비정상적으로 변형된다. 이러한 현상은 핫 캐리어(hot carrier) 효과의 감소와 소오스-드레인(source-drain) 간의 전기적 특성 개선을 위한 엘디디 구조 형성시 엘디디 구조내 이온 주입 농도 분포 및 콘택 홀 영역의 정확도를 저하시키는 요인으로 작용한다.The tungsten silicide layer 14 having a silicon composition ratio of 2 or more is a polysilicon layer as shown in FIG. 1 (b) during the thermal process performed after the gate patterning process due to such excessive silicon components. Silicon components segregate and crystallize at the interface between the 13 and the tungsten silicide layer 14 and the sidewalls of the tungsten silicide layer 14 to form a silicon precipitate 18. As such, since the tungsten silicide layer 14 is abnormally deformed, the spacer oxide film 17 formed in a subsequent process is also abnormally deformed. These phenomena lower the accuracy of contact hole region distribution and ion implant concentration distribution in the LED structure when the LED structure is formed to reduce the hot carrier effect and improve the electrical properties between the source and drain. Acts as.
즉, 텅스텐 폴리사이드 게이트(15)를 형성하기 위해 마스크 형성 공정, 플라즈마 건식 식각에 의한 게이트 패터닝 공정이 수반되며, 또한 엘디디 구조의 접합부를 형성하기 위해 스페이서 산화막 형성 공정이 진행된다. 이러한 공정으로 인하여 텅스텐 실리사이드층(14)의 조성 및 구조가 변화되는데, 특히 플라즈마 건식 식각에 의한 게이트 패터닝시 발생되는 불안정한 측벽쪽에 과도 실리콘 성분이 선택적으로 편석되어 불안정 부위의 계면 에너지를 저하시킨다. 이러한 편석은 스페이서 산화막(17) 형성 과정에서 결정화되어 텅스텐 실리사이드층(14)의 측벽에 돌출 형태의 실리콘 석출물(18)이 형성된다. 이 실리콘 석출물(18)로 인하여 스페이서 산화막(17)이 비정상적으로 돌출되게 변형된다. 그러므로 엘디디 구조 형성시 이와 같은 비정상적인 스페이서 산화막(17)의 돌출 부위로 인하여 고농도 이온주입 영역(19)와 저농도 이온주입 영역(16)의 교차점이 변화된다. 또한 스페이서 산화막(17)이 돌출되는 비정상적인 변형은 이후 공정에서 콘택 홀 영역을 정의하는데 문제점으로 작용한다.That is, a mask forming process and a gate patterning process by plasma dry etching are involved to form the tungsten polyside gate 15, and a spacer oxide film forming process is performed to form a junction of the LED structure. Due to this process, the composition and structure of the tungsten silicide layer 14 are changed. In particular, the transient silicon component is selectively segregated on the unstable sidewalls generated during gate patterning by plasma dry etching, thereby lowering the interfacial energy of the unstable portion. This segregation is crystallized in the process of forming the spacer oxide film 17, thereby forming a silicon precipitate 18 having a protruding shape on the sidewall of the tungsten silicide layer 14. This silicon precipitate 18 deforms the spacer oxide film 17 to protrude abnormally. Therefore, when the LED structure is formed, the intersection of the high concentration ion implantation region 19 and the low concentration ion implantation region 16 is changed due to the abnormal protrusion of the spacer oxide layer 17. In addition, abnormal deformation of the spacer oxide layer 17 protruding may cause a problem in defining the contact hole region in a subsequent process.
따라서, 본 발명은 금속 폴리사이드 구조를 적용하는 게이트에서 금속 실리사이드층의 구조적 결함이 발생하는 계면 부위에 선택적으로 과도 실리콘 성분이 편석되는 것을 방지하여 금속 실리사이드층의 열적 안정성을 향상시키고 공정을 안정화 시키는데 그 목적이 있다.Accordingly, the present invention improves the thermal stability of the metal silicide layer and stabilizes the process by preventing excessive silicon components from segregating selectively at the interface site where structural defects of the metal silicide layer occur in the gate to which the metal polyside structure is applied. The purpose is.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은, 반도체 기판 상의 선택된 영역에 폴리실리콘층 및 금속 실리사이드층으로 된 금속 폴리사이드 게이트를 형성하는 단계와, 상기 게이트 양측의 상기 반도체 기판 상에 저농도 이온주입 영역을 형성하는 단계와, 상기 금속 실리사이드층의 열적 및 물리적 안정성이 확보되도록 불활성 가스 분위기에서 프리-어닐링 공정을 실시하는 단계와, 상기 게이트의 양측벽에 스페이서 산화막을 형성한 후, 고농도 이온주입 영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a metal polyside gate including a polysilicon layer and a metal silicide layer in a selected region on a semiconductor substrate; Forming a low concentration ion implantation region on the substrate, performing a pre-annealing process in an inert gas atmosphere to ensure thermal and physical stability of the metal silicide layer, and forming spacer oxide films on both sidewalls of the gate. And forming a high concentration ion implantation region.
도 1(a) 및 도 1(b)는 종래의 방법에 의한 반도체 소자의 제조 방법을 설명하기 위한 단면도.1 (a) and 1 (b) are cross-sectional views for explaining a method for manufacturing a semiconductor device by a conventional method.
도 2(a) 및 도 2(b)는 본 발명에 의한 반도체 소자의 제조 방법을 설명하기 위한 단면도.2 (a) and 2 (b) are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the present invention.
＜도면의 주요 부분에 대한 부호 설명＞<Explanation of symbols on the main parts of the drawing>
11 및 21 : 반도체 기판 12 및 22 : 게이트 산화막11 and 21: semiconductor substrate 12 and 22: gate oxide film
13 및 23 : 폴리실리콘층 14 및 24 : 텅스텐 실리사이드층13 and 23: polysilicon layer 14 and 24: tungsten silicide layer
15 및 25 : 텅스텐 폴리사이드 게이트15 and 25: tungsten polyside gate
16 및 26 : 저농도 이온주입 영역16 and 26: low concentration ion implantation zone
17 및 27 : 스페이서 산화막 18 : 실리콘 석출물17 and 27: spacer oxide film 18: silicon precipitate
19 및 28 : 고농도 이온주입 영역19 and 28: high concentration ion implantation zone
20 : 이온주입 농도 교차점20: ion implantation concentration intersection
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 및 도 2(b)는 본 발명에 의한 반도체 소자의 제조 방법을 설명하기 위한 단면도이다.2 (a) and 2 (b) are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the present invention.
일반적으로 타이타늄 또는 텅스텐 폴리사이드 게이트를 형성하기 위한 고온에서 진행되는 여러 가지 열 공정에 의하여 금속 실리사이드층의 결정 구조는 육방격자 구조에서 정방격자 구조로 변화된다. 이러한 결정 구조의 변화 과정에서 원자의 충진 형태가 크게 변화되고 과도한 실리콘이 안정된 위치로 이동되는 조성적 변화가 수반된다. 또한 반응성 플라즈마에 의한 게이트 패터닝 공정시 플라즈마 구성 이온이 식각 표면으로 운동량을 전달하므로 금속 실리사이드층의 측벽은 결함이 다수 포함된 불안정한 상태가 된다. 이러한 금속 폴리사이드 게이트에 스페이서 산화막을 증착하면 계면 에너지를 낮추기 위해 구조적 결함이 존재하는 금속 실리사이드층의 측벽으로 과도 실리콘이 편석되고 결정화되어 실리콘 석출물이 형성된다.. 이와 같은 이유로 스페이서 산화막의 증착 토폴로지(topology)를 비정상적으로 변화 시킨다.In general, the crystal structure of the metal silicide layer is changed from a hexagonal lattice structure to a square lattice structure by various thermal processes performed at a high temperature to form a titanium or tungsten polyside gate. This change in crystal structure entails a significant change in the form of packing of atoms and a shift in the composition of excess silicon to a stable position. In addition, since the plasma constituent ions transfer momentum to the etching surface during the gate patterning process by the reactive plasma, the sidewall of the metal silicide layer is in an unstable state in which many defects are included. When the spacer oxide film is deposited on the metal polyside gate, excessive silicon is segregated and crystallized to form sidewalls of the metal silicide layer where structural defects exist in order to lower the interfacial energy. Thus, the deposition topology of the spacer oxide film ( changes the topology abnormally.
그러므로 과도 실리콘이 편석되고 결정화되는 주요 인자인 금속 실리사이드층 측벽의 구조적 결함을 회복시켜 주는 것이 본 발명의 가장 중요한 기술이다.Therefore, it is the most important technique of the present invention to recover the structural defects of the sidewalls of the metal silicide layer, which are the main factors for the transient silicon to segregate and crystallize.
도 2(a)에 도시된 것과 같이, 반도체 기판(21) 상에 50∼100Å 두께의 게이트 산화막(22), 500∼1000Å 두께의 폴리실리콘층(23) 및 500∼1000Å 두께의 텅스텐 실리사이드층(24)을 순차적으로 형성한 후 패터닝하여, 폴리실리콘층(23)과 텅스텐 실리사이드층(24)이 적층된 텅스텐 폴리사이드 게이트(25)를 형성한다. 이때 폴리실리콘층(23)은 SiH4와 PH3가스가 1.1:1.5∼1.5:1.8의 비율로 혼합된 가스를 사용하여 500∼700℃의 온도영역에서 화학기상증착법(CVD)으로 형성된다. 또한 텅스텐 실리사이드층(24)은 SiH2Cl2와 WF6가스가 2∼3 : 1∼1.5의 비율로 혼합된 가스를 사용하여 500∼650℃의 온도영역에서 화학기상증착법으로 형성된다. 한편 텅스텐 실리사이드층(24)내 실리콘의 화학론적 당량비는 하부의 폴리실리콘층(23)과의 접착강도 증가와 산화특성의 향상을 위하여 2∼2.8이 되도록 한다.As shown in FIG. 2A, a gate oxide film 22 having a thickness of 50 to 100 kPa, a polysilicon layer 23 having a thickness of 500 to 1000 kPa, and a tungsten silicide layer having a thickness of 500 to 1000 kPa are formed on the semiconductor substrate 21 ( 24 is sequentially formed and then patterned to form a tungsten polyside gate 25 in which the polysilicon layer 23 and the tungsten silicide layer 24 are laminated. At this time, the polysilicon layer 23 is formed by chemical vapor deposition (CVD) in a temperature range of 500 to 700 ° C using a gas in which SiH 4 and PH 3 gas are mixed at a ratio of 1.1: 1.5 to 1.5: 1.8. The tungsten silicide layer 24 is formed by chemical vapor deposition in a temperature range of 500 to 650 ° C. using a gas in which SiH 2 Cl 2 and WF 6 gas are mixed at a ratio of 2-3 to 1 to 1.5. On the other hand, the chemical equivalent ratio of silicon in the tungsten silicide layer 24 is set to 2 to 2.8 in order to increase the adhesive strength with the lower polysilicon layer 23 and to improve the oxidation characteristics.
텅스텐 폴리사이드 게이트(25)는 텅스텐 실리사이드층(24) 상부에 마스크 산화막을 증착한 후 플라즈마 건식 식각 공정으로 마스크 산화막 패턴을 형성하고, 마스크 산화막 패턴을 이용한 식각 공정으로 형성된다.The tungsten polyside gate 25 is formed by depositing a mask oxide layer on the tungsten silicide layer 24, forming a mask oxide layer pattern by a plasma dry etching process, and an etching process using a mask oxide layer pattern.
텅스텐 실리사이드층(24)은 600∼900℃에서 진행되는 게이트 형성을 위한 마스크 산화막 패턴 형성 과정에서, 그 결정구조가 육방격자 구조에서 정방격자 구조로 변화되며, 원자충진 형태가 크게 변화되어 내부의 과도 실리콘 원자가 안정된 위치로 이동되는 조성적 변화가 수반된다. 따라서 위와같은 원인의 텅스텐 실리사이드층(24) 측벽의 구조적 결함을 회복시켜 주기 위하여 프리-어닐링(pre-annealing) 공정을 실시한다.In the tungsten silicide layer 24, the crystal structure is changed from a hexagonal lattice structure to a square lattice structure in the process of forming a mask oxide film pattern for forming a gate at 600 to 900 ° C. It is accompanied by a compositional change in which silicon atoms are moved to a stable position. Therefore, a pre-annealing process is performed to recover structural defects of the sidewalls of the tungsten silicide layer 24 of the above cause.
즉, 텅스텐 폴리사이드 게이트(25) 양측의 반도체 기판(21) 상에, 도 2(b)에 도시된 것과 같이, 저농도 이온주입 공정으로 저농도 이온주입 영역(26)을 형성한 후, 텅스텐 실리사이드층(24) 측벽의 구조적 결함을 회복시켜 주기 위하여, 불활성 가스(N2및 Ar) 분위기의 600∼800℃의 온도 영역에서 15분∼30분동안 프리-어닐링 공정을 실시한다. 프리-어닐링 공정은 텅스텐 실리사이드층(24)의 전체 응력을 구성하는 열 응력과 소재 및 박막 구조에 관련된 인트린식 스트레스(intrinsic stress) 중 열 응력 성분을 107내지 108dyne/㎠ 이하로 감소시켜, 결과적으로 전체 응력 저하로 인한 열적 물리적 안정성의 확보를 이룰 수 있다. 이와 같이 안정성이 확보된 게이트의 양측벽에 스페이서 산화막(27)을 형성하면 그 단면적 변화율이 약 1∼3% 미만으로 제어된다. 이때 스페이서 산화막(27)은 장입온도를 300∼500℃로 제어하고, 700∼850℃의 온도 영역에서 SiH2Cl2+ N2O 또는 SiH4+ N2O 가스를 이용한 화학기상증착법으로 500∼1000Å의 두께가 되도록 형성한다. 이후 공정으로 고농도 이온주입 공정으로 고농도 이온주입 영역(28)을 형성하여, 저농도 및 고농도 이온주입 영역(26 및 28)으로 된 엘디디 구조의 접합부가 형성된다. 이때 저농도 이온주입 영역(26)과 고농도 이온주입 영역(28)의 교차점 변화율은 스페이서 산화막(27)의 단면적 변화율에 따라 1∼3% 미만으로 제어된다. 또한 이후 콘택 홀 형성 공정에 있어서도 정확하게 콘택 홀 영역을 정의할 수 있다.That is, after the low concentration ion implantation region 26 is formed on the semiconductor substrate 21 on both sides of the tungsten polyside gate 25 by the low concentration ion implantation process, the tungsten silicide layer is formed. (24) In order to recover structural defects of the sidewalls, a pre-annealing process is carried out for 15 to 30 minutes in a temperature range of 600 to 800 ° C in an inert gas (N 2 and Ar) atmosphere. The pre-annealing process reduces the thermal stress component in the thermal stress constituting the total stress of the tungsten silicide layer 24 and the intrinsic stress related to the material and the thin film structure to 10 7 to 10 8 dyne / cm 2 or less. As a result, it is possible to secure thermal and physical stability due to the decrease in overall stress. When the spacer oxide film 27 is formed on both side walls of the gate in which the stability is secured in this manner, the rate of change of the cross-sectional area is controlled to less than about 1 to 3%. At this time, the spacer oxide film 27 controls the charging temperature to 300 ~ 500 ℃, 500 ~ 500 by chemical vapor deposition using SiH 2 Cl 2 + N 2 O or SiH 4 + N 2 O gas in the temperature range of 700 ~ 850 ℃ It is formed to have a thickness of 1000Å. Subsequently, the high concentration ion implantation region 28 is formed by the high concentration ion implantation process to form a junction of the LED structure having the low concentration and the high concentration ion implantation regions 26 and 28. At this time, the rate of change of the intersection of the low concentration ion implantation region 26 and the high concentration ion implantation region 28 is controlled to less than 1% to 3% according to the change rate of the cross-sectional area of the spacer oxide film 27. In addition, the contact hole region may be precisely defined in the subsequent contact hole forming process.
상술한 바와 같이 본 발명에 의하면, 금속 폴리사이드 게이트 형성 후 프레-어닐링 공정을 추가함으로써 금속 실리사이드층 측벽의 구조적 결함이 회복되어 비정상 변형이 억제된다. 따라서 스페이서 산화막 형성시 증착 토폴로지 변화가 배제되므로, 엘디디 구조의 접합부 형성시 이온 주입 농도 분포 영역의 정확도가 배가되어 트랜지스터의 특성이 향상되고, 콘택 홀 영역을 정확하게 정의할 수 있어 콘택 저항의 균일도가 향상되는 탁월한 효과가 있다.As described above, according to the present invention, by adding a pre-annealing process after forming the metal polyside gate, structural defects of the metal silicide layer sidewalls are recovered, and abnormal deformation is suppressed. Therefore, since the deposition topology is excluded when forming the spacer oxide layer, the accuracy of the ion implantation concentration distribution region is doubled when the junction of the LED structure is formed, thereby improving the characteristics of the transistor and accurately defining the contact hole region, thereby improving the uniformity of the contact resistance. There is an excellent effect to be improved.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980019182A KR100265228B1 (en) | 1998-05-27 | 1998-05-27 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980019182A KR100265228B1 (en) | 1998-05-27 | 1998-05-27 | Method for fabricating semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990086276A KR19990086276A (en) | 1999-12-15 |
| KR100265228B1 true KR100265228B1 (en) | 2000-09-15 |
Family
ID=19537789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980019182A KR100265228B1 (en) | 1998-05-27 | 1998-05-27 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100265228B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100549572B1 (en) * | 1999-12-15 | 2006-02-08 | 주식회사 하이닉스반도체 | Method for forming transistor provided with buffer layer for LDD screen |
-
1998
- 1998-05-27 KR KR1019980019182A patent/KR100265228B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990086276A (en) | 1999-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5364803A (en) | Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure | |
| KR100298970B1 (en) | Silicon Integrated Circuit Manufacturing Method | |
| JP4295922B2 (en) | Gas immersion laser annealing method suitable for application in the fabrication of small integrated circuits | |
| KR100530401B1 (en) | Semiconductor device having a low-resistance gate electrode | |
| US5652156A (en) | Layered polysilicon deposition method | |
| JP3168421B2 (en) | Method for manufacturing semiconductor device | |
| WO2001041544A2 (en) | Deposition of gate stacks including silicon germanium layers | |
| KR100456314B1 (en) | Method for forming gate electrode in semiconductor deivce | |
| US5087322A (en) | Selective metallization for high temperature semiconductors | |
| KR960005801A (en) | Semiconductor device manufacturing method | |
| KR100265228B1 (en) | Method for fabricating semiconductor device | |
| US5731226A (en) | Low temperature method of manufacturing epitaxial titanium silicide | |
| KR100743618B1 (en) | Gate of semiconductor and method for manufacturing the same | |
| GB2344693A (en) | Tungsten silicide nitride as an electrode for tantalum pentoxide devices | |
| JPH09139360A (en) | Metal wiring formation of semiconductor element | |
| KR100282436B1 (en) | Method for manufacturing of semiconductor device | |
| KR20010002668A (en) | Method for forming conductivity line of semiconductor device | |
| JPH10125617A (en) | Method of manufacturing semiconductor device | |
| KR100370156B1 (en) | method for manufacturing of semiconductor device | |
| KR100721203B1 (en) | Semiconductor device having ternary system oxide gate insulating layer and method of fabricating the same | |
| JPH0778991A (en) | Semiconductor device and fabrication thereof | |
| JPH0536911A (en) | Three-dimensional circuit element and manufacture thereof | |
| KR100500935B1 (en) | Method for manufacturing semiconductor device using tungsten film formed by physical vapor deposition as diffusion barrier | |
| KR20030048206A (en) | Method for forming gate of semiconductor device | |
| JPH03166737A (en) | Manufacture of thin-film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110526 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |