JPS6142966A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accelerate by forming in advance an N type channel layer on a semi-insulating GaAs substrate surface, sequentially depositing Ta, Pt, Au as gate metals and an insulating layer thereon, and then lifting off the GaAs layer and the Au-Ge layer to form source and drain. CONSTITUTION:After Si ions are implated to channel layer regions 3, 4 on the surface of a GaAs substrate 1 with a mask 2, the mask 2 is removed. A plasma CVDSiN film 5 is coated on the surface of the substrate 1, implanting atoms are activated, the film 5 is then removed, and a Ta layer 6, a Pt layer 7, an Au layer 8 and an SiO2 film are sequentially deposited. Then, a resist pattern 10 is formed, with the pattern as a mask the SiO2 layer 9 and the Au layer 8 are etched, and then the layers 6, 7 are ion etched to form a gate pattern. Subsequently, an N<+> type GaAs layer is grown on the surface of the substrate 1. Then, an Au-Ge, Ni film 14, an n<+> type GaAs layer 12 are selectively removed on the region 15 except the FET region, and an electric connection is performed by wiring electrode 6 made of Ta, Pt, Au.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method for manufacturing a semiconductor device such as an FET having a Schottky barrier gate formed by a metal-semiconductor junction.

<Prior art> GaAS has an electron mobility 4 to 5 times greater than that of Sj, and a semi-insulating high-resistance substrate can be obtained.
It is expected to be used as a material for ET and high-speed memory ICs. However, GaAs has low hole mobility and high surface state density, so it is not suitable for manufacturing bipolar transistors and MOSFETs due to the Fermi level tunneling effect, but rather Schottky barrier gates using metal-semiconductor junctions. F ET (Metal-
5en+1conductorFET or less MESFET
) have been prototyped and manufactured. MBSFE
When creating high-frequency transistors or high-speed memory ICs using T, the cutoff frequency is determined by the product of gate capacitance and source resistance, so it is necessary to reduce gate capacitance and source resistance to improve high speed. be. The gate capacitance is determined by the substrate carrier concentration, gate length, and gate length.・The width is determined from the operating characteristics of the FET. Therefore, shortening the gate length is an issue, but extreme shortening of the gate length cannot be achieved due to process constraints and consideration of increased gate resistance. On the other hand, in order to reduce the source resistance, it is necessary to form a highly doped layer near the gate to reduce the resistance of the source-gate channel layer and the contact resistance.

Therefore, conventional methods for manufacturing image source resistors of GaAs MESFETs are roughly divided into two methods. One is a method using an epitaxial wafer, and the other is a method using selective ion implantation. The former method uses semi-insulating Ga in advance.
An undoped layer +
This method uses a wafer on which nJ=, n+ Jt5 are sequentially epitaxially grown. Like this Q O+YI
A u -Q on the surface of the n'' layer using a
After selectively forming an e-ohmic electrode, and then using photolithography to selectively remove a portion between the source and drain using chemical etching or dry etching, the exposed n'N Form a gate electrode.

The structure of an FET based on this method is called a recessed structure, and is usually a known method. However, a recessed structure FE
When creating T, it is extremely difficult to selectively etching an extremely narrow local region of the N4 layer from submicron to about 2 μm with good controllability and uniformity within the wafer surface, so the controllability of the pinch-off voltage of the FET There are many problems in terms of uniformity of device characteristics and improvement in yield, and it cannot be said to be an excellent manufacturing method.

Therefore, recessed MESFETs are not often used, especially in the production of devices such as logic devices that require strict control of threshold voltage. -Force-selective ion implantation is considered as an excellent method for controlling pinch-off voltage and dark value voltage. In this method, to reduce the source resistance, n4
When selectively forming layers, it is preferable that the boundary between the n1 layer and n[ is as close to the gate as possible. The reality is that it is extremely difficult to perform mask alignment for gate formation in the gap between the n''li layer on the side and the n4 layer on the drain side, and it is difficult to expect reproducibility of characteristics or improvement in yield.

On the other hand, WS is used as a heat-resistant Ge1-'M pole in advance.
A method has been proposed in which a high melting point metal such as ix or WTix is formed and selective ion implantation of the n0 layer is performed in a self-aligned manner using the gate as a mask. However, the annealing temperature range for activating ion-implanted atoms to form the n+ layer is 800°.
It is close to C, and even when high-melting point metals are used, the characteristics of the Schottky barrier gate are not deteriorated and the reproducibility is maintained <n”J.
It is difficult to perform W annealing. Furthermore, when performing ion implantation to form the n9 layer, the implanted atoms are generally LSS
According to the theory, they are distributed not only in the depth direction, but also in the lateral direction in an area comparable to the projected range, so the implanted atoms wrap around directly under the gate, causing a decrease in breakdown voltage and fluctuations in dark value voltage. This is extremely inconvenient in terms of manufacturing. Furthermore, deterioration of element characteristics due to deterioration of the insulating substrate caused by the two-time heat treatment process also poses a problem.

OBJECTIVES> An object of the present invention is to eliminate the drawbacks of the above-mentioned conventional techniques and provide a method for manufacturing a semiconductor device that can operate at high speed with low source resistance.

Structure> The present invention involves forming an n-type channel layer on the surface of a semi-insulating GaAS substrate in advance, and then sequentially depositing a high melting point metal, a barrier metal, and a noble metal as a gate metal on the substrate, and then forming an insulating film thereon. , the high melting point metal other than the gate region using the insulating film as a mask.

Etching and removing barrier metal and precious metal multilayer films,
The high melting point metal and the barrier metal are undercut to form a Schottky gate, and the exposed Q a '
, n” QaAsJi was grown on the surface of the A s channel layer at low temperature using molecular beam epitaxial method, and then A
After depositing the u-Ge Ohmifuku electrode layer, the insulating film is etched to form the GaAs layer and A
This is a method for manufacturing a semiconductor device characterized by forming a source and a drain in a self-aligned manner by lifting off u-G e N.

<Example> FIGS. 1 to 6 are cross-sectional views of a semiconductor device in each step of the implementation method of the present invention.

In this example, the n-channel layer was formed using an ion implantation method that provides excellent uniformity of carrier concentration within the wafer surface. The GaAs substrate 1 used is an LEL method <100> orientation undoped GaAs substrate. Prior to the selective ion implantation of the n eyebrows, the substrate 1 was chemically etched in advance to remove a layer damaged by polishing or the like and contaminants, and then washed with pure water and dried.

Thereafter, using the photoresist mask 2, St ions are selectively implanted into desired regions 3 and 4 that will become the channel layer of the FET, and then the photoresist mask 2 is removed using oxygen plasma. The acceleration energy during ion implantation is 1
At 00 keV, the doses of SL ions to the normally-off FET region 3 and the normally-on FET region 4 are 1.5 XIO"cIII-z and +3X, respectively.
Then, as shown in Section 2'', the surface of the substrate 1 was coated with a plasma CVD 5=Nx film 5 to a thickness of 500 to 700 layers, and soo'c.

Annealing was performed for 20 minutes in a N2 stream to activate the implanted atoms. After forming the n-channel layer, the annealed plasma CVD 5jN film 5 is removed using buffered HF, and as shown in FIG. 3, TaFt6. PtJLi+7°AuFf8. S=
029 respectively film thickness + 0.3 #I11 + 0.3μ
m, 0.6 μtrr, and 0.4 μm.

The sputtering pressure during vapor deposition of 'l'a, Pt, and Au was 7 x 10-'' tons and Ar was 2.5 tO2.
Chemical sputtering was performed using Ar+02 (5% layer) at a sputtering pressure of 5×IQton. Thereafter, a resist pattern 10 was formed using photolithography to form a gate electrode. Photoresist is AZ-135
0J was used. The length of the gate was 1 μR1, the length of the gate was 1 μm, and the inside of the gate was 20 μm. Subsequently, as shown in FIG. 4, the 5L02 layer 9 is reactively etched using CF4+02 gas using the photoresist pattern 10 as a mask, the Au layer 8 is etched using Bcz3 gas, and then the Au layer 8 is etched using CF4+Q2 gas. PT layer 17. TaJFi6 is reactively etched to form a gate bomb. pt layer7. TaJi6 serves as a mask during etching A u N8, S
= 02 N 9 is undercut by 0.2 μm. The amount of undercut can be controlled by the etching time. Thus, Ta with 5L02 formed on the surface
/ P t / A u gate is Qa7!1. It will be formed on the s-substrate 1. Subsequently, after cleaning the surface of the GaAs substrate 1, as shown in FIG.
If grown to a thickness of 0.3 μm. Growth temperature is 54
The temperature was set to 0'C, and the flux of As to Ga was set to 10. The growth rate is 1 μm/h. S for dopant
i was used. The carrier concentration of the n1 layer is 5X10IPcJ
11'. In the case of molecular beam epitaxial growth, the exposed surface 11 of the G5As substrate 1 has n ” GaAs
I*12 is grown evixically, but on the 5tO2 layer a on the gate is a polycrystalline G a A s J Hibiki 13
grows. Ga.

The As and SL molecular beams have strong directivity, and "1" a6°Pt7 is undercut, so the 5L02 layer 9.
Due to the shadow effect of the Au layer 8, the n+GaAs layer 12 is
TaJ'#6. It can be formed accurately near the metal without contacting the Pt layer 7.

In addition, Ta and Pt are grown at a growth temperature of 550°C or lower.

Each layer of Au 6, 7 . "8 is stable, and no diffusion of electrode metal into the nGaAs layers 3 and 4 formed by ion implantation is observed, so no thermal deterioration of the Schottky gate is observed.n" After the growth of the GaAs layer 12, The GaAs substrate 1 is taken out from the molecular beam epitaxial apparatus, and the source,
An ohmic electrode that will become a drain is formed. The ohmic electrode 14 is formed by depositing Au-Ge (12 wt%) and NL to film thicknesses of 0.15 μm and 0.05 μm, respectively, using an electron beam evaporation method. Thereafter, the 5tO2 layer 9 on the gate is dissolved using buffered HF (HF:NH4F:H20=5:35:60). When melting 5
The polycrystalline GaAs layer 13 on the j02 layer 9 and the Au-Ge layer of the ohmic electrode 14 are lifted off at the same time. In addition, buffered HF has a low concentration of HF, so the Ta gate is
There is no f&. After removing the 5L02 layer 9, pure P
; After cleaning the GaAs substrate 1, Au Ge
, N=N14 and n+In order to obtain ohmic properties of GaAsJW12, heat treatment is performed at 430°C for 1 minute in a N2 stream. Subsequently, as shown in FIG. 6, the polylithography method,
And A u -Ge on the region 15 other than the FET region using the Ar ion milling method, N=14. n”Ga
A'sJ#12 is selectively removed to electrically isolate each FET. Electrical connections between the FETs can be made using wiring electrodes 16 made of Ta, Pt, and Au formed by electron beam evaporation and lift-off.

When the manufacturing method described above is used, the distance between the gate and the source can be controlled in a substantially self-aligned manner, and the contact resistance of the electrode can be reduced due to the 01 layer. In the example, the source resistance of the normally-off type FET and the normally-on type FET is extremely small, 0.2 Ω/mm and 0.1 Ω/mm per unit gate, respectively, and the yield within the wafer surface is also excellent. In the example, Ga is used for the gate electrode.
Ta, which has a coefficient of thermal expansion close to that of Ta, was used, but W and T were used to the extent that the Schottky characteristics did not deteriorate at about the n″′ layer growth temperature.
It is possible to use a general high melting point metal such as L, and there is no need to use a very special high melting point metal alloy or silicide that can withstand annealing after ion implantation at around 800°C.

<Effects> With the above configuration, the present invention can control the distance between the gate and the source in a self-aligned manner. In addition, a high-concentration n-layer can be formed in the vicinity of the gate using the gate electrode as a mask at a relatively low temperature, and dispersion of FET characteristics within the substrate plane can be suppressed.Therefore, high-speed semiconductor devices can be produced with high yield and stability. We can provide quality.

[Brief explanation of drawings]

1 to 6 are cross-sectional views of a semiconductor device at each manufacturing step in the method of implementing the present invention. 1.--GaAs substrate 3, 4-.-channel layer 6
-Ta layer 7-PtN 8--Au layer 9-5 b O2R 12--n'' Ga As layer 13--polycrystalline GaAs layer 14--Ohmic electrode tooth

Claims (1)

[Claims] An n-type channel layer is formed in advance on the surface of a semi-insulating GaAs substrate, a high melting point metal, a barrier metal, and a noble metal are sequentially deposited on the substrate as a gate metal, and an insulating film is formed thereon, and then the insulating film is masked. As a step, the metal multilayer film of the high melting point metal, barrier metal, and noble metal other than the gate region is etched away, and the high melting point metal and barrier metal are undercut to form a Schottky gate, and the exposed surface of the GaAs channel layer is removed. The n^+ GaAs layer was grown at low temperature using the molecular beam epitaxial method, and then A
After depositing the u-Ge ohmic electrode layer, the insulating film is etched to remove the GaAs layer and Au-G on the insulating film.
1. A method of manufacturing a semiconductor device, comprising lifting off an e-layer to form a source and a drain in a self-aligned manner.