JPS63260178A - Manufacture of nonvolatile memory element - Google Patents

Abstract

PURPOSE:To prevent the formation of a parasitic tapered gate MOS transistor by forming an element region by selective oxidation and a field region, removing one part of an silicon oxide film in the field region through etching and etching a bird bear section in the periphery of the element region. CONSTITUTION:A specific region in a first conductivity type semiconductor substrate 1 is used as an element region 2, and an silicon oxide film is formed into a field region 3 in the periphery of the element region 2 and a first conductivity type concentrated diffusion layer 4 to the semiconductor substrate 1 in the field region 3. One part of the silicon oxide film in the field region 3 is removed through etching, and an silicon oxide film partially used as a memory gate insulating film 5 is shaped onto the surface of the element region 2. An silicon nitride film 6 and a memory gate electrode 8 are formed onto the memory gate insulating film 5, and second conductivity type source region and drain region are shaped, employing the memory electrode 8 as a mask. An insulating film for a multilayer interconnection mainly comprising the silicon oxide film is formed, a contact window is shaped by using a photoetching technique, and a wiring metal is formed. Accordingly, the leakage currents by a parasitic tapered gate MOS transistor are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a nonvolatile memory element, and relates to improvement, stabilization, and high reliability of memory characteristics.

[Conventional technology and its problems]

In the manufacturing process of a nonvolatile memory element, a specific region of a semiconductor substrate having a first conductivity type is used as an element region, and 7. A thick silicon oxide film is formed in the yield region by selective oxidation.

Through this selective oxidation step, a tapered silicon oxide film called a bird's beak is formed between the element region and the field region. After that, a thin silicon oxide film is formed on the surface of the element region, a part of which will become a memory gate insulating film, and a silicon nitride film and a polycrystalline silicon film, a part of which will become a memory gate electrode, are formed on this memory gate insulating film. , a source region and a drain region of the second conductivity type are formed using the memory gate electrode as a mask. By applying a sufficiently high positive voltage for a short time to the memory gate electrode of the nonvolatile memory element obtained by this manufacturing method, electrons in the conductor of the semiconductor substrate pass through the memory gate insulating film due to the tunnel effect, and the memory gate It is captured in the level at the interface between the insulating film and the silicon nitride film. As a result, negative charges are accumulated in the silicon nitride film, and the threshold voltage changes. Memory characteristics are obtained from this phenomenon.

The nonvolatile memory element manufactured by the method described above has the following problems.

A parasitic taper (MOS) transistor is formed in the bird's beak portion generated in the selective oxidation process. In a state where negative charges are accumulated in the silicon nitride film of the nonvolatile memory element manufactured by the above method, the threshold voltage of the element region is high. If a voltage is gradually applied to the memory gate electrode in this state, the threshold voltage is high in the element region, so it is difficult for current to flow, but in the Taber gate MOS transistor, current flows at a low applied voltage. This results in leakage current.

An example is shown in FIG. 2(a). In the relationship between the gate voltage (VGS) and drain current (IDS) of a memory transistor, the drain current flows at a low gate voltage.

Due to the above-mentioned reason, there is a problem in that the write/erase width becomes narrow due to the memory characteristics.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a nonvolatile memory element that reduces leakage current caused by a parasitic tapered gate MOS transistor and has stable memory characteristics.

[Means for solving problems]

For the above purpose, in the present invention, after forming an element region and a field region by selective oxidation, a part of the silicon oxide film in the field region is etched and removed, and a bird's beak portion around the element region is etched to form a parasitic taper gate MOS transistor. prevent.

〔Example〕

The present invention will be described in detail below using the drawings.

FIGS. 1A to 1D are longitudinal sectional views of a memory gate electrode of a memory transistor of a nonvolatile memory element in each step of an embodiment of the present invention.

First, as shown in FIG. 1(a), a specific region of a first conductivity type semiconductor substrate 1 is defined as an element region 2, and an ion implantation amount I is applied to a field region 3 around the element region by an ion implantation method.
A first conductivity type impurity of approximately X 10"cm is implanted, and a dense diffusion layer 4 and a silicon oxide film having a thickness of approximately 1.2 .mu.m are formed by selective oxidation.

Next, as shown in FIG. 1(b), the surface of the silicon oxide film in the field region 3 is etched to a thickness of about 0.3 μm and removed, thereby exposing the dense diffusion layer 4.

Next, as shown in FIG. 1C, a memory gate insulating film 5 made of a silicon oxide film with a thickness of about 3 mm is formed on the surface of the element region in an oxidizing atmosphere. Thereafter, a silicon nitride film 6 with a thickness of about 1 5 nm and a polycrystalline silicon film 7 with a thickness of about 500 nm as a memory gate electrode are deposited on the entire surface by CVD.

Next, as shown in FIG. 1(d), a memory gate electrode 8 is formed using photoetching technology, and using the memory gate electrode 8 as a mask, 4X is formed by ion implantation.
Ion implantation with a thickness of about 10''cm4 is performed to form source and drain regions of the second conductivity type.

After this, a multilayer wiring insulating film mainly made of silicon oxide is formed using a general method, a contact window is formed using photoetching technology, and aluminum is formed as the wiring metal to form a non-volatile layer. A sexual memory element is obtained.

In the present invention, since the bird's beak portion where the parasitic taper gate MOS transistor is formed is located on the dense diffusion layer, the threshold voltage of the parasitic taper gate MOS transistor becomes high. As a result, the conventional leakage current as shown in FIG. 2(a) is suppressed as shown in FIG. 2(b), resulting in stable memory characteristics.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the current in the parasitic tapered gate MOS transistor is significantly reduced.

Figure 2(b) shows an example of this, and the conventional leakage current shown in Figure 2(a) does not occur in the relationship between the memory gate applied voltage and drain current of a nonvolatile memory element. do not have. And the leakage current is reduced K
Therefore, when a voltage is applied to the memory gate electrode, the memory characteristics are more enhanced, the write width is increased, and the application time is shortened compared to the conventional one. That is,
Write/erase time is shortened.

According to the manufacturing method of the present invention, memory characteristics can be improved and stabilized, and a highly reliable nonvolatile memory element can be obtained.

[Brief explanation of drawings]

Figures 1(a) to 2 are cross-sectional views of a nonvolatile memory element in each step of an embodiment of the present invention, and Figure 2(a) shows memory gate voltage-drain current characteristics of a conventional nonvolatile memory element. The graph in FIG. 2(b) is a graph showing the memory gate voltage-drain current characteristics of the nonvolatile i-storage element according to the present invention. 2...Element region, 3...Field region, 4...Dense diffusion layer, 5...Memory gate insulating film, 6... Silicon nitride film, 8...
・Memory gate electrode. Figure 2 VGS (Vl

Claims (1)

[Claims] forming a silicon oxide film in a field region around the device region and a dense diffusion layer of a first conductivity type in the semiconductor substrate in the field region; a step of etching and removing a portion of the silicon oxide film in the field region; a step of forming a silicon oxide film, a portion of which will become a memory gate insulating film, on the surface of the element region; and a step of etching a silicon oxide film on the memory gate insulating film. a step of forming a ride film and a memory gate electrode; a step of forming a source region and a drain region of a second conductivity type using the memory electrode as a mask;
A non-volatile memory element comprising the steps of forming an insulating film for multilayer wiring mainly composed of a silicon oxide film, forming a contact window using photo-etching technology, and forming a wiring metal. manufacturing method.