JPS63255959A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a latch-up phenomenon even when a power source is turned on by a method wherein the output terminal of a substrate bias generating circuit is short-circuited to a grounding level for the prescribed period after the power source has been turned on. CONSTITUTION:An N-channel type MOS transistor Q3 and a resistor R5, which is inserted between the gate of the transistor Q3 and the output terminal PBB of a substrate bias generating circuit, are provided. At this point, a high level pulse signal is generated for the prescribed period after a power source is turned on. As voltage is applied to the gate of the transistor Q3 through the intermediary of a capacitor C2, the transistor Q3 is brought into a conductive state for the prescribed period immediately after the power source is turned on, and the main section (time t2-t3), in which the potential VPB of the output terminal PBB shows a positive value, is forcedly clamped to an 0V. Consequently, the occurrence of a latch-up phenomenon can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular to a 0MO3
The present invention relates to prevention of wrap-up when power is turned on in a semiconductor integrated circuit device having a structure.

[Conventional technology]

FIG. 5 is a sectional view of a conventional semiconductor integrated circuit device such as a CMOS type dynamic RAM. In the figure, 1 is a P-type semiconductor substrate, and an N-well region 2 is formed on this P-type semiconductor substrate 1. In this N-well region 2, P+
type semiconductor regions 3 and 4 are formed, and P+ type conductor regions 3 and 4 are formed.
N-well territory in between! A base electrode 5 is provided above P
The +-type semiconductor regions 3 and 4 are each connected to a power supply V. . , output terminal OU
By connecting the input terminal IN to the base mill 5, a P-channel MOS transistor 6 is formed. In addition, 7 is an N+ type hemihyposome region, and N- well region 2
It is provided to bias the voltage to the power supply Vco level.

On the other hand, an N+ type flat conductor region 89 is provided on the P type semiconductor substrate 1, and the P type semiconductor substrate 1 is provided between the N'' type semiconductor regions 1a8.9.
A base electrode 10 is provided above, and a gap-shaped semiconductor region 8.9 is formed.
are connected to the ground level vS3 and the output terminal OUT, respectively, and the base electrode 10 is connected to the input terminal IN, thereby forming an N-channel type MO8I-transistor 11. In addition,
Reference numeral 12 denotes a P' type semiconductor region, which is provided to bias the P type semiconductor substrate 1 to the bias potential VBB level. In a normal RAM or the like, this bias potential VBB is a negative voltage (approximately -3V) supplied from an on-chip voltage generation circuit provided on the same radix 1.

Incidentally, in a semiconductor integrated circuit device as shown in FIG. 5, a phenomenon called latch-up is likely to occur. Latch-up is indicated by the broken line arrow in Figure 5, J, and power supply V. C
This is a phenomenon in which a large current of several tens of mA constantly flows from the ground level to the ground level v3s. The cause of this latch-up occurrence will be explained below.

FIG. 6 is a circuit diagram showing an equivalent circuit of the parasitic bipolar transistor of the semiconductor integrated circuit device having the structure shown in FIG. In the same figure, R1 is the diffused resistance of the P゛ type semiconductor region 143, R2 is the diffused resistance of the N+ type semiconductor region 7, and R3 is the resistance of the output terminal of the bias potential vBB and the P+ type semiconductor region 1.
The combined resistance of the diffused resistances of llt12 and R4 are the diffused resistances of the N+ type semiconductor region 1iit8. Moreover, Ql is a P+ type semiconductor region 3. N-well region 2. A parasitic PNP type bipolar transistor formed by a P type semiconductor substrate 1, Q
2 is the N-well region 2. P-type semiconductor substrate 1. This is an anomalous NPN bipolar transistor composed of an N+ type semiconductor region 8. This parasitic transistor Q1. Because Q2 exists, when the potential at point P1 takes a positive value at a certain moment and exceeds the on-voltage of parasitic transistor Q2, parasitic transistor Q2 becomes conductive. The power supply V is connected through the connection, resistor R2, strange transistor Q2, and resistor R4. When a current flows from 0 to ground level 33, the base voltage of the parasitic transistor Q1 decreases, and the parasitic transistor Q1 becomes conductive. Then, even more strange transistor Q
The base potential of Q2 increases, and the current flowing through the parasitic transistor Q2 increases. In this way, the parasitic transistor Q1
．． When a positive feedback loop is formed by Q2, the power supply V constantly increases. A large current flows from 0 to ground level v88, and in the worst case, it may lead to destruction. Such a latch-up phenomenon does not normally occur because the bias potential vBB is biased to a negative voltage as described above, so that the parasitic transistor Q2 does not become conductive.

[Problem that the invention seeks to solve]

However, the power supply■. 0 and the bias potential VBB due to many junction capacitances formed on the P-type semiconductor substrate 1, a capacitor C1 shown in FIG. 6 is formed.

Furthermore, since the bias potential VBB is supplied by an on-chip power generation circuit formed on the P-type semiconductor substrate 1, it is O when the power is turned on, and a predetermined potential (-
3V), it takes several hundred μsec. This situation is shown in t in Figure 7, which shows the power supply ■. FIG. 2 is a timing chart showing the temporal change of 0 and the temporal change of the potential v, 1 applied to the point P1. As shown in the figure, the reason why the potential P1 applied to the point P1 takes a positive value immediately after the power is turned on is due to capacitive coupling by the capacitor C1 shown in FIG. This positive voltage value is the parasitic transistor Q in Figure 6.
When the on-voltage exceeds No. 2, the latch-up phenomenon described above occurs. As a result, the potential VP1 at point P1 continues to maintain a positive voltage value as shown by the broken line in FIG. 7, and this semiconductor integrated circuit device not only cannot operate normally, but also has problems such as destruction. There was a point.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor integrated circuit device that does not cause latch-up even when the power is turned off.

[Means for solving problems]

A semiconductor integrated circuit device according to the present invention has a substrate bias generation circuit formed on the same semiconductor substrate, and has a source connected to an output terminal of the substrate bias generation circuit, and a drain connected to a ground level. - a transistor, a resistor inserted between the gate of the transistor and the output terminal of the substrate bias circuit; and pulse signal generating means.

[Effect]

The pulse generating circuit of the present invention generates a high-level pulse signal only for a predetermined period after power is turned on. Therefore, by applying a voltage to the gate of the transistor via a capacitor, the transistor is activated at a predetermined level immediately after power is turned on. Since the output terminal of the substrate bias generation circuit is conductive for only a period and the output terminal of the substrate bias generation circuit is short-circuited to the ground level, the output terminal of the substrate bias generation circuit does not show a positive value during that period.

〔Example〕

FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention, and is a circuit diagram particularly showing a short circuit between a ground level v88 and an output terminal 188 of a substrate bias generation circuit. In the same figure, Q3 has a drain at a ground level vss, and a source at an output terminal PB of a substrate bias generation circuit (not shown).
R5 is a resistor inserted into the gate of the transistor Q3 and the output terminal P8- of the substrate bias generation circuit.

Also, POR is the power supply V. This is a one-shot pulse generated by the pulse generation circuit shown in FIG. 2 when a zero is input. This signal FOR is supplied to the gate of transistor Q3 via capacitor C2.

FIG. 2 is a circuit diagram showing a pulse generation circuit for signal POR. As shown in the figure, the output signal of an inverter G1 consisting of a P-channel MOS transistor Q5 and an N-channel IMOS transistor Q6 is P and OR. In addition, the input terminal P2 of the inverter G1 and the power supply V. . A resistor R6 is inserted between them, and a capacitor C3 is inserted between this input terminal P2 and the tI ground level v88, and this resistor R6 and capacitor C3 serve as a time constant that determines the voltage applied to the terminal P2.

FIG. 3 is a timing diagram showing the operation of the circuit of FIG. 2. When the power supply V rises at time t1, the voltage MV at terminal C2 follows the time constant CR from time t1,
Power supply ■ Increases more slowly than cc. After that, at time t2, the power supply ■ is turned on. When the voltage value of 0 exceeds the drive voltage ■dr of the inverter G1, the inverter G1 is driven. At this time, the potential V,2 of terminal P2 is still at the "L" level (
Since VF6<VGl (threshold voltage of inverter G1)), the signal PO
R is the power supply V. It becomes equal to the value of 0, and thereafter the power supply ■ is turned on until time t3. Makes the same change as 0.

Then, at time t3, when v, 2>Vol is reached, the output of inverter G1 is inverted, and signal POR is at "L" level (
OV), and the potential level of the signal POR does not change thereafter.

FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 1. The operation will be explained below with reference to FIGS. 1 and 4. Power supply V at time t1. 0 rises, and the signal POR rises at time t2 as shown in FIG. This signal POR
When the voltage reaches the "H" level, a "H" voltage is applied to the capacitor C2, and the potential at the point P3 rises due to capacitive coupling, but at the same time, the charge at the point P3 is discharged through the resistor R5.

At this time, by setting the resistance value of the resistor R5 to a large value, it is possible to cause a voltage exceeding the threshold voltage of the transistor Q3 to appear at the point P3 in response to the pulse generation of the signal POR.

In addition, the power supply is generally ■. The slower the rise of 0, the more latch-up is likely to occur, but in this case, the timing of the rise of the signal POR becomes earlier and its wave i tlfi also becomes higher, so there is no problem in use.

For the reason mentioned above, when the signal POR rises, the transistor Q3 becomes conductive, and the output terminal PBB of the substrate bias generation circuit (not shown) and the ground level V88 are short-circuited.
The potential ■PB of the output terminal P is forcibly clamped to Ov. From then on, as shown by the solid line, O
V is maintained until the signal POR falls at time t3. For reference, the potential change of the output terminal PBB in the conventional case (when there is no short circuit) is shown by a broken line.

Then, at time t3, the signal POR falls, and as a result, the point P3 becomes Ov, so the transistor Q3 becomes non-conductive, and the output terminal PBB and the ground level VSS are cut off. After this, the normal drive of the on-chip substrate bias generation circuit is transmitted to the output terminal PBB, and the potential VP of the terminal P
B changes as shown in Figure 4, and eventually approaches V88 (-3V).

During this time, the gate potential of transistor Q3 does not rise above the voltage value during that time, so transistor Q3 does not become conductive, and the output terminal P and the ground level V are connected again.
Since B 88 is never short-circuited, the potential vPB of the output terminal P reaches the bias potential VB 88 (-3V).

In this way, the main section (old system t''-t3) where the potential VPB of the output terminal P shows a positive value B is forced to 0.
(2) Since it is clamped at 1, no latch-up phenomenon occurs. Moreover, it can be realized with a relatively simple circuit configuration as shown in the short-circuit circuit shown in FIG. 1 and the pulse generation circuit shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, the output terminal of the substrate bias generation circuit is short-circuited to the ground level for a predetermined period after the power is turned on, so that the latch-up phenomenon does not occur even when the power is turned on. You can get the equipment.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a short circuit between the ground level 38 of a semiconductor integrated circuit device according to an embodiment of the present invention and the output terminal 288 of a substrate bias generation circuit, and FIG. A circuit diagram of a pulse generation circuit of a certain semiconductor integrated circuit device, FIG. 3 is a timing diagram showing the operation of the circuit in FIG. 2, FIG. 4 is a timing diagram showing the operation of the circuit in FIG. 1,
FIG. 5 is a cross-sectional view of a conventional CMOS type dynamic RAM 8 semiconductor integrated circuit device, FIG. 6 is a circuit diagram showing an equivalent circuit of the anomalous bipolar transistor of the semiconductor integrated circuit device of FIG. 5, and FIG. 7 is a timing diagram showing the operation of the circuit of FIG. 6 immediately after power is turned on; FIG. In the figure, 03 is an N-channel type MO8t-transistor;
■ is the ground level, P8B1. is the substrate bias source S main circuit output terminal, POR is the pulse signal, and C2 is the key 1? pacita, R5 is a resistor. Note that in each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a CMOS type semiconductor integrated circuit device including a substrate bias generation circuit formed on the same semiconductor substrate, an N-channel MOS whose source is connected to the output terminal of the substrate bias generation circuit and whose drain is connected to the ground level.
a transistor; a resistor inserted between the gate of the transistor and the output end of the substrate bias circuit; and a pulse signal that is at a high level for a predetermined period after power is turned on and is applied to the gate of the transistor via a capacitor. A semiconductor integrated circuit device comprising a pulse signal generating means.