JPS63255958A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a latch-up phenomenon even when a power source is turned on by a method wherein the output terminal of a substrate bias generating circuit is short-circuited to a grounding level for the prescribed period after the power source has been turned on. CONSTITUTION:The title integrated circuit has the first N-channel type MOS transistor Q3 and the second N-channel type MOS transistor Q4 having the threshold voltage lower than that of the transistor Q3. At this point, a high level pulse signal is generated during the prescribed period after a power source is turned on. As high level voltage is applied to the gate of the first transistor Q3 through the intermediary of a capacitor 2, the first transistor Q3 becomes conductive for the prescribed period immediately after the power source is turned on, and the main section (time t2-t3), in which the potential VPB of an output terminal PBB indicates a positive value, is forcedly clamped 0V. Consequently, the occurrence of a latch-up phenomenon can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a 0MO8
The present invention relates to prevention of latch-up when power is turned on in a semiconductor integrated circuit device having a structure.

[Conventional technology]

FIG. 5 is a sectional view of a conventional semiconductor integrated circuit device such as a CMOS type dynamic RAM. In the figure, reference numeral 1 denotes a P-type semicircular substrate, and an N-well region 2 is formed on this P-type semiconductor substrate 1. In this N-well region 2, P+
A type semiconductor region 13.4 is formed, and a P+ type semiconductor region 3,4 is formed.
A base electrode 5 is provided above the N-well region 2 between the P+
The type semiconductor regions 3.4 are each connected to a power supply V. o1 output terminal OUT
By connecting the input terminal IN to the base electrode 5, a P-channel MOS transistor 6 is formed. Note that 7 is an N+ type semiconductor region, which is provided to bias the N- well region 2 to the power supply Vcc level.

On the other hand, an N+ type semiconductor region 8.9 is provided on the P type semiconductor substrate 1, a base electrode 10@ is provided above the P type semiconductor substrate 1 between the N+ type semiconductor regions 8.9, and the N゛ type semiconductor region 8.9 is Each of them is connected to the ground level v83 and the output terminal OUT, and the base electrode 10 is connected to the input terminal IN, thereby forming an N-channel MOS transistor 11. In addition, 12
is a P+ type semiconductor region, which is provided to bias the P type semiconductor substrate 1 to the bias potential VBB level. This bias potential ■BB is, in a normal RAM, etc.
This is a negative voltage (approximately -3V) supplied from an on-chip voltage generation circuit provided on the same substrate 1.

Incidentally, in a semiconductor integrated circuit device as shown in FIG. 5, a phenomenon called latch-up is likely to occur. Latch-up is a phenomenon in which a large current of several tens of milliamps (C) constantly flows from the power source (1) to the ground level (83) as shown by the broken line arrow in FIG.

The cause of this latch-up occurrence will be explained below.

FIG. 6 is a circuit diagram showing an equivalent circuit of the parasitic bipolar transistor of the semiconductor integrated circuit device having the structure shown in FIG. In the figure, R1 is the diffused resistance of the P+ type semiconductor region 3, R2 is the diffused resistance of the N+ type semiconductor region 11117, and R3 is the diffused resistance of the N+ type semiconductor region 11117.
is the combined resistance of the resistance of the output terminal of the bias potential BB and the diffused resistance of the P+ type semiconductor region hit12, and R4 is the diffused resistance of the N+ type semiconductor region 8. Moreover, Ql is a P+ type semiconductor region 3. N-"Shell region 2. Strange PNP type bipolar transistor formed by P type semiconductor substrate 1, Q2
is the N-well region 2. P-type semiconductor substrate 1. This is an anomalous NPN bipolar transistor composed of an N+ type semiconductor region 8. This strange transistor Q1. Because Q2 exists, when the potential at point P1 takes a positive value at a certain moment and exceeds the on-voltage of parasitic transistor Q2, parasitic transistor Q2 becomes conductive. As a result, the power supply V is applied via the resistor R2, the parasitic transistor Q2, and the resistor R4. 0 to the ground level V88, the base voltage of the parasitic transistor Q1 decreases, and the parasitic transistor Q
1 is conductive. Then, the base potential of the parasitic transistor Q2 further increases, and the current flowing through the parasitic transistor Q2 increases. In this way, the parasitic transistor Q1.
When a positive feedback loop is formed by Q2, the power supply ■ continues. A large current flows from 0 to ground level VS8, and in the worst case, it may lead to destruction. Such a latch-up phenomenon does not normally occur because the bias potential BB is biased to a negative voltage as described above, so that the parasitic transistor Q2 does not become conductive.

[Problem that the invention seeks to solve]

However, due to many junction capacitances formed on the P-type semiconductor substrate 1, a capacitor C1 shown in FIG. 6 is formed between the power supply vcc and the bias potential vBB.

In addition, since the bias potential V8B is supplied by an on-chip power generation circuit formed on the P-type semiconductor substrate 1, it is O■ when the power is turned on, and the predetermined potential (
-3V), it takes several hundred μsec. This situation is shown at t in FIG. 7, which shows the power supply V. 2 is a timing chart showing the temporal change of the voltage 0 and the temporal change of the potential ■P1 applied to the point P1. FIG. As shown in the figure, the reason why the potential ■P1 applied to the point P1 takes a positive value immediately after the power is turned on is due to the Furukawa coupling caused by the capacitor C1 shown in FIG. When this positive voltage value exceeds the on-voltage of the parasitic transistor Q2 shown in FIG. 6, the latch-up phenomenon described above occurs. As a result, the potential ■, 1 at point P1 continues to maintain a positive voltage value as shown by the broken line in FIG. 7, and this semiconductor integrated circuit device not only cannot operate normally, but may even be destroyed. There was a problem.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor integrated circuit device that does not cause latch-up even when the power is turned on.

[Means for solving problems]

A semiconductor integrated circuit device according to the present invention has a substrate bias generation circuit formed on the same semiconductor substrate, and a first N channel in which a source is connected to an output terminal of the substrate bias generation circuit, and a train is connected to a ground level. Type MO3t
- a transistor, whose source is the output terminal of the substrate bias generation circuit, and whose drain is the gate of the first transistor;
a second N-channel MOS whose threshold voltage is lower than that of the first transistor, each having its gate connected to a ground level;
The first transistor is configured to include a transistor and a pulse generation circuit that applies a pulse signal that remains at a high level for a predetermined period of time after power is turned on to the gate of the first transistor via a capacitor.

[Effect]

Since the pulse generation circuit of the present invention generates a high-level pulse signal only for a predetermined period after power is turned on, a high-level voltage is applied to the gate of the first transistor via the capacitor, and the first transistor lasts only for a predetermined period immediately after the electrode is applied, and since the output terminal of the substrate bias generation circuit is short-circuited to the ground level, the output terminal of the substrate bias generation circuit does not show a positive value during that period.

〔Example〕

FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention, and is a circuit diagram showing, in particular, a short circuit between the ground level vS8 and the output terminals P and - of the substrate bias generation circuit. In the figure, Q3 is a first N-channel MOS transistor whose drain is connected to the ground level V,8 and its source is connected to the output terminal P88 of a substrate bias generation circuit (not shown), and Q4 is a first N-channel MOS transistor whose source is connected to the output terminal P88 of a substrate bias generation circuit (not shown). Output terminal PBB1 drain is connected to the gate of transistor Q3,
a second N-channel MOS whose threshold voltage is lower than that of transistor Q3, whose gates are connected to ground levels V and S, respectively;
It is a transistor. Further, POR is a one-shot pulse generated by the pulse generating circuit shown in FIG. 2 when the power supply (i)oC is turned on. This signal FOR is supplied to the gate of transistor Q3 and the train of transistor Q4 via capacitor C2.

FIG. 2 is a circuit diagram showing a pulse generation circuit for signal POR. As shown in the figure, the output signal of an inverter G1 consisting of a P channel type MOS transistor Q5 and an N:f channel type MOS transistor Q6 is POR. In addition, the input terminal P2 of the inverter G1 and the power supply V. A resistor R5 is inserted between the input terminal P2 and the ground level V, and a capacitor C3 is inserted between the input terminal P2 and the ground level V, and the capacitor C3 becomes a time constant that determines the voltage applied to the terminal P2.

FIG. 3 is a timing diagram showing the operation of the circuit of FIG. 2. When the power supply ■ starts up at time t1, the voltage of the output terminal P2 (+Q V is the time constant CR from time t1
Accordingly, the voltage rises more slowly than the power supply ■cc. After that, turn on the power at the time [■. The voltage value of 0 is invert G
1, the inverter G] is driven. At this time, the potential V,2 of terminal P2 is at the lowest level (Vp2<Vol (threshold voltage of inverter G1))
Therefore, since the transistor Q5 is conductive, the signal POR becomes the power supply ■. becomes equal to the value of 0, and thereafter at time t3
Power until ■. Makes the same change as 0.

Then, at time t, when V,2>V61, the output of invert G1 is inverted, and signal POR is at the "L" level (
OV), and the potential level of the signal POR does not change thereafter.

FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 1. The operation will be explained below with reference to FIGS. 1 and 4. Power supply V at time t1. 0 rises, and the signal FOR rises at time t2 as shown in FIG. This signal FOR
When the voltage reaches the HQ level, “H” is applied to the capacitor C2, and the potential vP3 at the point P3 becomes the signal POR due to capacitive coupling.
Since it shows almost the same value as , transistor Q3 becomes conductive and
Since the output terminal PBB of the substrate bias generation circuit (not shown) and the ground level v, 8 are short-circuited, the potentials (1), 8 of the output terminal PBB are forcibly clamped to OV. Thereafter, as shown by the solid line, Ov is maintained until the signal POR falls at time t3. For reference, the change in potential VPB of the output terminal PB8 in the conventional case (in the case of no short circuit) is shown by a broken line. Note that the base potential of the transistor Q4 is fixed at OV, and its source potential, ie, ■, B, does not become negative during the time period t-t3, so the transistor Q4 remains non-conductive during that time.

Then, at time t3, the signal POR falls, and the point P3 becomes OV.
Therefore, the transistor Q3 becomes non-conductive, and the output terminal PBB and the ground level v88 are cut off. After this, the normal drive of the on-chip substrate bias generation circuit is transmitted to the output terminal P8B, and the potential VPB of the terminal P begins to fall below Ov and approaches vBBB (-3V).

As potential VPB decreases, transistor Q4 becomes conductive when IV, 81 exceeds the threshold voltage of transistor Q4. As a result, the potential VP3 at the point P3 becomes a negative potential following the change in the potential VPB, and finally the bias potential V8
8 (-3V). Therefore, transistor Q3 does not become conductive, and output terminal PBB and ground level v88 are connected again.
is never shorted. This is because the IaJ1 direct voltage of the transistor Q4 is set lower than the threshold tri voltage of the transistor Q3, so the transistor Q4 always becomes conductive first.

In this way, the potential vPB of the output terminal P has a positive value,
Since the main section (times 12 to 13) indicating B is forcibly clamped to OV, no latch-up phenomenon occurs. Moreover, it can be realized with a relatively simple circuit configuration as shown in the short-circuit circuit shown in FIG. 1 and the pulse generation circuit shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, the output terminal of the substrate bias generation circuit is short-circuited to the ground level for a predetermined period after the power is turned on, so that the latch-up phenomenon does not occur even when the power is turned on. You can get the equipment.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a short circuit between the ground level v38 of a semiconductor integrated circuit device and the output terminal 188 of a substrate bias generation circuit, which is an embodiment of the present invention, and FIG. 2 is an embodiment of the present invention. A circuit diagram of a pulse generation circuit of a semiconductor integrated circuit device, FIG. 3 is a timing diagram showing the operation of the circuit in FIG. 2, FIG. 4 is a timing diagram showing the operation of the circuit in FIG. 1,
FIG. 5 is a cross-sectional view of a conventional semiconductor integrated circuit device such as a CMOS type dynamic RAM, FIG. 6 is a circuit diagram showing an equivalent circuit of a parasitic bipolar transistor of the semiconductor integrated circuit device of FIG. 5, and FIG. 7 is a timing diagram showing the operation immediately after power is turned on in the circuit of FIG. 6. FIG. In the figure 03. C4 is an N-channel MOS transistor, 2 is a ground level, PBB is an output terminal of a substrate bias generation circuit, POR is a pulse signal, and C2 is a capacitor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 't11t21t3ginr Figure 4: ;: t+t2t3 Moment Figure 5 Figure 6 111 and -Vss Figure 7 Self-motivated to write procedural amendments)

Claims (1)

[Claims] (1) In a CMOS type semiconductor integrated circuit device having a substrate bias generation circuit formed on the same semiconductor substrate, a first N-channel whose source is connected to the output terminal of the substrate bias generation circuit and its drain is connected to the ground level. Type M
an OS transistor, and a second N-channel MOS having a lower threshold voltage than the first transistor, the source of which is connected to the output terminal of the substrate bias generation circuit, the drain to the gate of the first transistor, and the gate to a ground level. 1. A semiconductor integrated circuit device comprising: a transistor; and a pulse generation circuit configured to apply a pulse signal that remains at a high level for a predetermined period of time after power is turned on to the gate of the first transistor via a capacitor.