JPS63253671A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remove anisotropic etching, controllability of which is difficult, to simplify a process and to improve reliability by forming a high melting-point metallic silicide layer onto the surface of an element forming region, using an silicon nitride film coating only a polycrystalline silicon film selectively shaped as a mask. CONSTITUTION:A gate insulating film 3 is formed onto the surface of an element forming region shaped to one main surface of a P-type silicon substrate 1. A polycrystalline silicon film 4 is formed selectively onto the film 3, and an silicon nitride film 5 is shaped only onto the surface of the film 4 through a method of thermal nitridation. A polycrystalline silicon film 6 as a control gate electrode is formed choicely onto the film 5. The gate insulating film 3 is removed through etching, employing the silicon nitride film 5 as a mask to expose the surface of the element forming region. A titanium film is deposited onto the whole surface through a sputtering method, and a titanium silicide film 8 is shaped through heat treatment. An unreacted titanium film 7 is gotten rid of. A polycrystalline silicon film 4 is formed and used as a floating gate electrode, and an N-type diffusion region 9 is shaped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a floating gate electrode.

[Conventional technology]

MO3 structure EPROM with floating gate electrode (e
rasable programmable read
only memory) has the advantage that data can be easily written by the device manufacturer and the contents of the data can be easily changed.

FIGS. 2(a) to 2(h) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

As shown in FIG. 2(a), a field insulating film 2 for element isolation is formed on one principal surface of a P-type silicon substrate 1 to define an element formation region, and a gate insulating film is formed on the surface of the element formation region. A polycrystalline silicon film 4 with a thickness of 0.4 μm is selectively formed on the gate insulating film 3, and a polycrystalline silicon film 4 with a thickness of 400 μm is formed by thermal oxidation.
A silicon oxide film 10 is formed.

Next, as shown in FIG. 2(b), a polycrystalline silicon film 6 is deposited on the entire surface to a thickness of 0.4 μm, and a photoresist film 11 is selectively provided on the polycrystalline silicon film 6.

Next, as shown in FIG. 2(c), the photoresist film 11
polycrystalline silicon film 6 and silicon oxide film 1 using as a mask.
0 and polycrystalline silicon film 4 are sequentially removed by etching, and polycrystalline silicon film 6 is used as a control gate electrode and polycrystalline silicon film 4 is used as a floating gate electrode. Next, using the photoresist film 11 and the field insulating film 2 as masks, arsenic is ion-implanted at an acceleration energy of 70 keV and a dose of 5 x 10"cm-2 to form an N-type diffusion region 9 in the element formation region, and the photoresist film 11 is removed. do.

Next, as shown in FIG. 2(d), a silicon oxide film 12 is deposited to a thickness of 0.1 μm over the entire surface by CVD.

Next, as shown in FIG. 2(e), by anisotropic etching, the silicon oxide film 12 is left only on the sidewalls of the laminated layer consisting of the polycrystalline silicon film 4, the silicon oxide film 10, and the polycrystalline silicon film 6, and , exposing the surface of the N-type diffusion region 9.

Next, as shown in Figure 2(f), titanium J was applied to the entire surface.
]5j7 is deposited to a thickness of 0.1 μm by sputtering.

Next, as shown in FIG. 2(g), a heat treatment is performed at 600° C. for 60 minutes to contact the polycrystalline silicon film 6 and the N-type diffusion region 9 and react with the titanium WA 7 to form a titanium silicide film 8. Form.

Next, as shown in FIG. 2(h), the unreacted titanium film 7 is removed using a hydrogen peroxide based etching solution.

[Problem that the invention seeks to solve]

In the conventional semiconductor device manufacturing method described above, a high melting point metal silicide film is formed on the surface of the diffusion region in order to reduce the resistance of the diffusion region to become the source and drain regions. It is necessary to form a silicon oxide film on the sidewalls of the floating gate electrode to prevent short circuits with the silicide film.

However, in order to form a silicon oxide film on the side walls of the floating gate electrode, the silicon oxide film formed by the CVD method is subjected to anisotropic etching that is difficult to control, leaving the silicon oxide film only on the side walls of the floating gate. However, there is a problem in that the silicon oxide film formed by the CVD method is damaged by the sputtering process for depositing the metal silicide film, resulting in a decrease in film quality.

An object of the present invention is to provide a semiconductor device that simplifies the process and has excellent reliability! i! The goal is to provide a way to send money.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes: (A) selectively forming a field insulating film for element isolation on one principal surface of a semiconductor substrate of one conductivity type to define an element formation region; A gate insulating film is formed on the surface, a first polycrystalline silicon film is deposited on the gate insulating film and selectively etched to form a floating gate electrode, and a silicon nitride film is formed to cover only the floating gate electrode. (B) depositing a second polycrystalline silicon film on the entire surface including the silicon nitride film, selectively etching it to form a control gate electrode, and etching the gate insulating film using the silicon nitride film as a mask; (C) Depositing a high melting point metal film over the entire surface and then heat-treating it so that it is in contact with the second polycrystalline silicon film and the element formation region; a step of reacting the high melting point metal film to form a high melting point metal silicide film and removing the unreacted high melting point metal film; (D) using the high melting point metal silicide film and field insulating film as a mask to form a high melting point metal silicide film; silicon film and the first
(E) forming the floating gate electrode self-aligned with the pattern of the second polycrystalline silicon film by sequentially etching the polycrystalline silicon film; (E) using the control gate electrode and the field insulating film as a mask; The method includes a step of ion-implanting impurities to form a diffusion region of an opposite conductivity type in the element formation region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
A field insulating film 2 for element isolation is formed on one principal surface to define an element forming region, a gate insulating WA3 is formed on the surface of the element forming region, and a film thickness of 0.4 mm is formed on the gate insulating film 3.
A polycrystalline silicon film 4 having a thickness of 400 μm is selectively formed, and a silicon nitride film 5 having a thickness of 400 μm is formed only on the surface of the polycrystalline silicon film 4 by thermal nitriding.

Next, as shown in FIG. 1(b), a polycrystalline silicon film 6 to become a control gate electrode is selectively provided on the silicon nitride film 5.

Next, as shown in FIG. 1(c), the gate insulating film 3 is removed by etching using the silicon nitride M5 as a mask to expose the surface of the element formation region.

Next, as shown in FIG. 1(d), a 0.1 μm titanium film is deposited on the entire surface by sputtering.

Next, as shown in FIG. 1(e), a heat treatment is performed at 600° C. for 60 minutes to cause the polycrystalline silicon film 6 and the titanium film 7 in contact with the exposed surface of the element formation region to react and become silicide. A titanium film 8 is formed.

Next, as shown in FIG. 1(f), the unreacted titanium film 7 is removed using a hydrogen peroxide-based etching solution.

Next, as shown in FIG. 1(g), a titanium silicide film 8
Using as a mask, silicon nitride film 5 and polycrystalline silicon film 4 are sequentially etched to form polycrystalline silicon film 4 that is self-aligned with polycrystalline silicon film 6 to form a floating gate electrode.

Next, using the polycrystalline silicon film 6 and the field insulation M2 as a mask, arsenic is ion-implanted at an acceleration energy of 7° keV and a dose of 5×10 cm −2 to form an N-type diffusion region 9 in the element formation region. .

〔Effect of the invention〕

As explained above, the present invention can be achieved by forming a high melting point metal silicide film on the surface of the element formation region using the silicon nitride film that covers only the selectively formed first polycrystalline silicon film as a mask. This has the effect of eliminating such anisotropic etching process which is difficult to control.

In addition, a poorly modified silicon nitride film affected by the sputtering process for depositing a high melting point metal can be removed, and a highly reliable semiconductor device can be manufactured.

Furthermore, since a high melting point metal silicide film can be formed on the side surfaces of the second polycrystalline silicon film constituting the control gate electrode, the control gate electrode has the effect of increasing its conductivity.

[Brief explanation of drawings]

1(a) to 1(g) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (h) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field insulating film, 3... Gate insulating film, 4... Polycrystalline silicon film,
5... Silicon nitride film, 6... Polycrystalline silicon film,
7...Titanium film, 8...Titanium silicide film, 9
... N-type diffusion region, 10 ... silicon oxide film, 11
... Photoresist film, 12... Silicon oxide film. ￥1 2 words

Claims (1)

[Scope of Claims] (A) A field insulating film for element isolation is selectively formed on one principal surface of a semiconductor substrate of one conductivity type to demarcate an element formation region, and gate insulation is provided on the surface of the element formation region. forming a floating gate electrode by depositing and selectively etching a first polycrystalline silicon film on the gate insulating film, and forming a silicon nitride film covering only the floating gate electrode; (B) A second polycrystalline silicon film is deposited on the entire surface including the silicon nitride film and selectively etched to form a control gate electrode, and the gate insulating film is etched and removed using the silicon nitride film as a mask. , exposing the surface of the element formation region; (C) depositing a high melting point metal film on the entire surface and then heat-treating the second polycrystalline silicon film and the high melting point metal in contact with the element formation region; a step of reacting the film to form a high melting point metal silicide film and removing the unreacted high melting point metal film; (E) forming the floating gate electrode self-aligned with the pattern of the second polycrystalline silicon film by sequentially etching the first polycrystalline silicon film; (E) etching the control gate electrode and the field insulating film; A method for manufacturing a semiconductor device, comprising the step of ion-implanting impurities as a mask to form a diffusion region of an opposite conductivity type in the element formation region.