JPS6068655A - Manufacture of mos transistor - Google Patents
Manufacture of mos transistorInfo
- Publication number
- JPS6068655A JPS6068655A JP17624083A JP17624083A JPS6068655A JP S6068655 A JPS6068655 A JP S6068655A JP 17624083 A JP17624083 A JP 17624083A JP 17624083 A JP17624083 A JP 17624083A JP S6068655 A JPS6068655 A JP S6068655A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon oxide
- silicon
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 16
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は、ＭＯ８型トランジスタの製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing an MO8 type transistor.
（従来技術）
従来のＭＯ８型トランジスタの製造方法を第１図を用い
て説明する。第１図（ａ）において、１１はシリコン基
板であり、まず、このシリコン基板１１の表面に６００
０〜９０００Ａのフィールド酸化膜１２を選択的に形成
することにより、シリコン基板１１上全フイールド領域
１３とアクティブ領域１４に分ける。(Prior Art) A conventional method for manufacturing an MO8 type transistor will be described with reference to FIG. In FIG. 1(a), 11 is a silicon substrate, and first, 600
By selectively forming a field oxide film 12 of 0 to 9000 Å, the entire silicon substrate 11 is divided into a field region 13 and an active region 14 .
ここで、フィールド酸化膜１２は減圧気相成長法による
図示しない窒化膜全マスクとした選択酸化法によって形
成される。Here, the field oxide film 12 is formed by a selective oxidation method using a nitride film (not shown) as an entire mask using a low pressure vapor phase growth method.
次に、８００〜１０００℃のドライ酸化によって、アク
ティブ領域１４（シリコン基板１１の露出表面）に第１
図（ｂ）に示すように２００〜５００Ａのシリコン酸化
膜１５を成長させる。Next, by dry oxidation at 800 to 1000°C, a first
As shown in Figure (b), a silicon oxide film 15 of 200 to 500 Å is grown.
その後、減圧気相成長法によって２０００〜４１Ｊ００
Ａの多結晶シリコン膜を成長させる。そして、この多結
晶シリコン膜全写真食刻法により、ゲート電極１６とな
る部３分のみ残してエツチング除去する。After that, 2000~41J00 was obtained by low pressure vapor phase growth method.
A polycrystalline silicon film is grown. Then, this entire polycrystalline silicon film is etched away by photolithography, leaving only three portions of the portion that will become the gate electrode 16.
さらに、これによる残存多結晶シリコン膜１６（ゲート
電極）全マスクとして、その下のゲート酸化膜となる部
分のみ残してシリコン酸化膜１５をエツチング除去する
。Furthermore, using this as a mask for the entire remaining polycrystalline silicon film 16 (gate electrode), the silicon oxide film 15 is removed by etching, leaving only the portion that will become the gate oxide film underneath.
次に、気相成長法によってシリコン基板全面にシリコン
酸化膜１７を２０００〜４０００Ｘ形成する。Next, a silicon oxide film 17 of 2000 to 4000× is formed on the entire surface of the silicon substrate by vapor phase growth.
この後、異方性エツチングにょシ、シリコン基板１１の
全体をシリコン酸化膜１７がなくなシ、シリコン基板１
１が現われるまでエツチングする。After that, anisotropic etching is performed to completely remove the silicon oxide film 17 from the silicon substrate 11.
Etch until 1 appears.
このとき、ゲート電極１６の側面に第１図（Ｑ）のよう
にシリコン酸化膜１７が残る。この後、イオン打込み法
によってＡｓ ｋ １０１６ｃｍ−２打ち込む。At this time, a silicon oxide film 17 remains on the side surface of the gate electrode 16 as shown in FIG. 1(Q). Thereafter, As k 1016 cm-2 is implanted by the ion implantation method.
次に、第１図（ｄＪのよりに、メタル１８ （ＭＯ＊Ｗ
、Ｔｔ、Ｔａなと）ｔｓ ｏ ｏ 〜１ｏ ｏ ｏＸ堆
積する。このメタルは数百度程度の温度でシリコンと容
易に反応しシリサイド（ケイ化物）を形成するものであ
る。Next, in Figure 1 (dJ), metal 18 (MO*W
, Tt, Ta) ts o o ~ 1 o o oX are deposited. This metal easily reacts with silicon to form silicide at a temperature of several hundred degrees.
次に、第１図（ｅ）に示すように、シリコン基板１１を
６００〜１０００ ’Ｃの不活性ガス中で熱処理を行い
、ゲート電極１６とソース・ドレイン領域上にシリサイ
ド１９を形成し、同時にＡｓ ｆ拡散さセソース管ドレ
イン拡散層１１０’ｉ作る。このとき、ゲート電極１６
の側面はシリコン酸化膜１７１でおおわれているため、
シリサイド化は起こらず、メタル？除去すればゲート電
極１６とソース・ドレイン領域は短絡しない。Next, as shown in FIG. 1(e), the silicon substrate 11 is heat-treated in an inert gas at 600 to 1000'C to form silicide 19 on the gate electrode 16 and the source/drain regions. As f diffused source tube drain diffusion layer 110'i is made. At this time, the gate electrode 16
Since the side surfaces of are covered with a silicon oxide film 171,
Silicidation does not occur and is it metal? If removed, the gate electrode 16 and the source/drain region will not be short-circuited.
この後、第１図（ｆ）に示すように、中間絶縁膜１１１
ｔ”形成し、コンタクト孔を開けＡｔ配線１１２’ｉ形
成し、ＭＯ８）ランジスタとする。After this, as shown in FIG. 1(f), the intermediate insulating film 111
A contact hole is formed, an At wiring 112'i is formed, and an MO8) transistor is formed.
このよりな従来の製造方法においては、ゲート電極１６
の側面に気相成長処よるシリコン酸化膜の異方性エツチ
ングによって、シリコン酸化［１７’の壁を形成し、こ
れをマスクとしてメタルとシリコンを反応させ、ゲート
電極１６ンース・ドレイン領域上にメタルシリサイドを
形成するものである。In this more conventional manufacturing method, the gate electrode 16
A wall of silicon oxide [17'] is formed by anisotropic etching of a silicon oxide film by vapor phase growth on the side surface of the gate electrode 16, and using this as a mask, metal and silicon are reacted, and a metal layer is formed on the gate electrode 16 and the source and drain regions. It forms silicide.
したがって、この壁であるシリコン酸化１１ｇ１７’の
横方向の厚さは膜厚（段差の亮さ）によって決まフ；０
．５〜１μｍ程度である。Therefore, the lateral thickness of this wall of silicon oxide 11g17' is determined by the film thickness (brightness of the step);
．． It is about 5 to 1 μm.
また、フィールド領域の側面にもシリコン酸化膜が残り
、アクティブ領域を狭くする欠点があった。最大の欠点
としては第２図に示したようにゲート配線２６の段差部
側面にもシリコン酸化膜２７が残ってしまい、段差部の
ゲート配線がシリサイド化されず、低抵抗化がさまたけ
られることがあった。In addition, the silicon oxide film remains on the side surfaces of the field region, which has the disadvantage of narrowing the active region. The biggest drawback is that, as shown in FIG. 2, the silicon oxide film 27 remains on the side surfaces of the stepped portion of the gate wiring 26, and the gate wiring at the stepped portion is not silicided, which prevents lowering the resistance. was there.
（発明の目的）
この発明は、これらの従来の欠点を除去するためになさ
れたもので、従来の異方性エツチングによるシリコン酸
化膜に比べて薄膜化が可能でかつ選択的にゲート電極側
面にのみ形成できるＭＯ８型トランジスタの製造方法を
提供すること全目的とする。(Purpose of the Invention) The present invention was made to eliminate these conventional drawbacks, and it is possible to make the film thinner than the silicon oxide film formed by conventional anisotropic etching, and to selectively coat the side surface of the gate electrode. The overall objective is to provide a method for manufacturing MO8 type transistors that can be formed only by using the following methods.
（発明の構成）
この発明のＭＯ８型トランジスタの製造方法は、シリコ
ン基板の表面に選択的にフィールド酸化膜を形成した後
、シリコン基板の露出表面に第１のシリコン酸化膜全形
成し、この第１のシリコン酸化膜上に多結晶シリコン膜
および第２のシリコン酸化膜を順次形成し、ゲート領域
のみ第２の酸化膜と多結晶シリコン膜を残してその他を
エツチングし、残存した多結晶シリコン膜の側面ｖｆ−
第１のシリコン窒化膜に変換した後、第２のシリコン酸
化膜を除去すると同時に残存した多結晶シリコン膜をマ
スクとしてその下取外の第１のシリコン酸化膜全除去し
、シリコン基板にソース・ドレイン拡散層全形成し、メ
タルの膜を堆積し、ゲート電極とソース中ドレイン領域
をシリサイド化するとともに未反応メタルのＭｋ線除去
、層間絶縁膜を全面に形成してこの眉間絶縁膜にコンタ
クト孔を形成して、配線するようにしたものである。(Structure of the Invention) The method for manufacturing an MO8 transistor of the present invention includes selectively forming a field oxide film on the surface of a silicon substrate, and then forming a first silicon oxide film on the entire exposed surface of the silicon substrate. A polycrystalline silicon film and a second silicon oxide film are sequentially formed on the first silicon oxide film, and the remaining polycrystalline silicon film is etched, leaving only the second oxide film and the polycrystalline silicon film in the gate region. Side view of vf-
After converting to the first silicon nitride film, the second silicon oxide film is removed, and at the same time, the remaining polycrystalline silicon film is used as a mask to completely remove the first silicon oxide film, and the source layer is placed on the silicon substrate. The entire drain diffusion layer is formed, a metal film is deposited, the gate electrode and the drain region in the source are silicided, the Mk line of unreacted metal is removed, an interlayer insulating film is formed on the entire surface, and a contact hole is formed in this insulating film between the eyebrows. It is designed to form and conduct wiring.
（実施例）
以下、この発明のＭＯ８型トランジスタの製造方法の実
施例について図面に基づき説明する。第３図（ａ）〜第
３図（ｄ）はその一実施例の工程説明図である。この発
明の工程は第１図（ａ）までは従来と同様であるので省
略する。(Example) Hereinafter, an example of the method for manufacturing an MO8 type transistor of the present invention will be described based on the drawings. FIG. 3(a) to FIG. 3(d) are process explanatory diagrams of one embodiment. The steps of the present invention up to FIG. 1(a) are the same as those of the prior art and will therefore be omitted.
第３図（ａ）はフィールド酸化膜３２を形成したシリコ
ン基板３１のアクティブ領域３４上にシリコン酸化膜３
５を８００〜１０００℃のドライ酸化によって２００〜
５００Ｘ形成し、ゲート膜とし、その上に減圧気相成長
法によって２０００〜４０００Ａの多結晶シリコンＭ３
６に成長させる。そしてこの多結晶シリコン膜３６上に
８００〜９００℃のドライ酸化によって１００〜２００
Ａのシリコン酸化膜３７を形成したものである。FIG. 3(a) shows a silicon oxide film 3 on an active region 34 of a silicon substrate 31 on which a field oxide film 32 is formed.
5 to 200~ by dry oxidation at 800~1000℃
Polycrystalline silicon M3 of 2000 to 4000A is formed on it by low pressure vapor phase growth method.
Grow to 6. Then, dry oxidation at 800 to 900°C is performed on this polycrystalline silicon film 36 to give a
A silicon oxide film 37 is formed.
次に、この多結晶シリコン膜３６とその上のシリコン酸
化膜３７全写真食刻法によって同時にゲート電極になる
べき部分を残し、ＣＦａガスを主としたエツチングによ
り除去する。これによシ、ゲート電極側面のみ多結晶シ
リコンが露出している。Next, the entire polycrystalline silicon film 36 and the silicon oxide film 37 thereon are removed by photoetching, leaving only a portion to become the gate electrode, by etching mainly using CFa gas. As a result, polycrystalline silicon is exposed only on the side surfaces of the gate electrode.
この後、第３図（ｂ）に示すように、このゲート電極側
面を多結晶シリコン膜３６上の薄いシリコン酸化膜３７
”ｉマスクとして１ｏｏｏ〜１２ｏｏ℃のＮＨ３中で熱
窒化し１００〜２００Ｘの熱窒化膜３８を形成する。After that, as shown in FIG. 3(b), the side surface of this gate electrode is covered with a thin silicon oxide film 37 on the polycrystalline silicon film 36.
``As an i-mask, thermal nitridation is performed in NH3 at 100 to 120°C to form a thermal nitride film 38 of 100 to 200X.
次に、第３図（ｅ）に示すように、イオン注入によって
、 Ａｓイオン全全面に〜ｌ ０１６ｃｒｎ−２打ち込
み、メタ／Ｉ／３９ （Ｍｏ ｌ ｗ、 ’ｒｉ Ｉ
Ｔａ など）全５００〜１０００Ｘ堆積する。Next, as shown in FIG. 3(e), by ion implantation, As ions were implanted into the entire surface, and meta/I/39 (Mol w, 'ri I
Ta, etc.) are deposited at a total of 500-1000X.
この後、第３図（ｄ） Ｋ示ｆｊうに、６００〜１００
０℃の不活性ガス中で熱処理を行い、ゲート電極および
ソース・ドレイン領域上にシリサイド３１０全形成し、
同時にＡｓ ｆ拡散させソース・ドレイン拡散層３１１
を作る。After this, as shown in Fig. 3(d), K fj is 600 to 100.
Heat treatment is performed in an inert gas at 0° C. to completely form silicide 310 on the gate electrode and source/drain regions,
At the same time, Asf is diffused into the source/drain diffusion layer 311.
make.
このとき、ゲート側面は熱窒化膜３８でおおわれている
ためシリサイド化は起こらず、未反応のメタルを除去す
ればゲート電極とソース・ドレイン領域は船路しない。At this time, since the side surfaces of the gate are covered with the thermal nitride film 38, silicidation does not occur, and if unreacted metal is removed, the gate electrode and the source/drain regions are not separated.
この後、中間絶縁膜を形成し、コンタクト孔を開けＡｔ
配線全形成しＭＯＳ）ランジスタとする。After this, an intermediate insulating film is formed and a contact hole is opened.
All wiring is formed to form a MOS transistor.
この実施例によれば、ゲート電極側面の壁が熱窒化膜で
あるために異方性エツチングを必要とせず、形成が容易
であシ、厚さも１００〜２００Ａと薄い。したがって素
子の微細化にとっても有オＵである。According to this embodiment, since the side wall of the gate electrode is a thermal nitride film, anisotropic etching is not required, the formation is easy, and the thickness is as thin as 100 to 200 Å. Therefore, it is also useful for miniaturization of elements.
また、ゲート電極の側面にしか窒化膜が形成されないた
め、アクティブ領域を狭くすることがなく、第２図のよ
うに段差部側面には窒化膜は形成されずシリサイド化さ
れ、ゲート配線の低抵抗化が計れる。In addition, since the nitride film is formed only on the side surfaces of the gate electrode, the active area is not narrowed, and as shown in Figure 2, the nitride film is not formed on the side surfaces of the stepped portion but is silicided, resulting in a low resistance of the gate wiring. can be measured.
（発明の効果）
以上のように、この発明のＭＯ８型トランジスタの製造
方法によれは、ゲート電極およびソース・ドレイン領域
のシリサイド化のマスクとしてゲート電極側面に熱窒化
膜を用いるようにしたので、従来の異方性エツチングに
よるシリコン酸化膜に比べて薄膜化が可能でるり、また
、選択的にゲート電極側面のみに形成することができる
利点がある。(Effects of the Invention) As described above, according to the method for manufacturing an MO8 type transistor of the present invention, a thermal nitride film is used on the side surface of the gate electrode as a mask for silicidation of the gate electrode and source/drain regions. It has the advantage that it can be made thinner than the conventional silicon oxide film formed by anisotropic etching, and that it can be selectively formed only on the side surfaces of the gate electrode.
第１図（ａＪ〜第１図（ｆ）は従来のＭＯ８型トランジ
スタの製造方法の工程説明図、第２囚は従来のＭＯ８型
トランジスタの製造方法で得られたＭＯ８型トランジス
タのゲート配線の段差部における低抵抗化の妨けとなる
ことを示す図、第３図（ａＪ〜第３図（ｄ）はこの発明
のＭＯ８型トランジスタの製造方法の一実施例の工程説
明図である。
３１・・・シリコン基板、３２・・・フィールド酸化膜
、３４・・・アクティブ領域、３５・・・ゲート絶縁膜
、３６・・・多結晶シリコン膜、３７′・・・シリコン
酸化膜、３８・・・熱窒化膜、３９・・・メタル、３１
０・・・シリサイド、３１１・・・ソース・ドレイン拡
散層。
特許出願人 沖電気工業株式会社
第１図 １３
第１図
第２図
手続補正書
昭和ｒ′９年１月１８日
特許庁長官若杉和夫 殿
１、事件の表示
昭和５８年 特 許 願第 １７６２４０ 号２、発明
の名称
ＭＯ８型トランジスタの夷遣方法
３、補正をする者
事件との関係 特 許 出願人
（０２９）沖電気工業株式会社
４、代理人
５、補正命令の日付 昭和 年 月 日 （自発）６、
補正の対象
第３図
ス偽Figure 1 (aJ to Figure 1 (f) are process explanatory diagrams of the conventional MO8 type transistor manufacturing method, and the second figure is a step difference in the gate wiring of the MO8 type transistor obtained by the conventional MO8 type transistor manufacturing method. 3(aJ to 3(d) are process explanatory diagrams of an embodiment of the method for manufacturing an MO8 type transistor of the present invention. 31. ...Silicon substrate, 32...Field oxide film, 34...Active region, 35...Gate insulating film, 36...Polycrystalline silicon film, 37'...Silicon oxide film, 38... Thermal nitride film, 39...Metal, 31
0...Silicide, 311...Source/drain diffusion layer. Patent Applicant Oki Electric Industry Co., Ltd. Figure 1 13 Figure 1 Figure 2 Procedural Amendment January 18, 1939 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1, Indication of Case 1982 Patent Application No. 176240 2. Title of the invention: Method of using MO8 type transistor 3. Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4. Agent 5. Date of amendment order Showa year, month, day (self-motivated) )6,
Target of correction: Figure 3 is false.
Claims (1)
しかつ前記シリコン基板の露出表面に第１のシリコン酸
化膜を形成する工程と、この第１のシリコン酸化膜上に
多結晶シリコン膜全形成しかつこの多結晶シリコン膜の
表面に第２のシリコン酸化膜を形成する工程と、ゲート
領域のみ第２のシリコン酸化膜および多結晶シリコン膜
を残しその他全エツチングする工程と、残存多結晶シリ
コン膜側面？第１の窒化膜に変換する工程と、第２のシ
リコン酸化膜全除去すると同時に残存多結晶シリコン膜
をマスクとしてその下取外の第１のシリコン酸化膜を除
去する工程と、シリコン基板にソース、ドレイン拡散層
を形成する工程と、金属膜を堆積しゲート電極およびソ
ース、ドレイン領域をシリサイド化し未反応メタルの膜
全除去する工程と、層間絶縁膜を全面に形成しその層間
絶縁膜にコンタクト孔を形成して配線を形成する工程と
全具備してなるＭＯ８型トランジスタの製造方法。selectively forming a field oxide film on the surface of the silicon substrate and forming a first silicon oxide film on the exposed surface of the silicon substrate; and forming a polycrystalline silicon film entirely on the first silicon oxide film. Also, a step of forming a second silicon oxide film on the surface of this polycrystalline silicon film, a step of etching all the other parts leaving only the second silicon oxide film and the polycrystalline silicon film in the gate region, and a step of etching the remaining polycrystalline silicon film on the side surface. ? A step of converting the silicon oxide film into a first nitride film, a step of completely removing the second silicon oxide film and simultaneously removing the first silicon oxide film that has been removed using the remaining polycrystalline silicon film as a mask, and a step of converting the first silicon oxide film into a silicon substrate. , a step of forming a drain diffusion layer, a step of depositing a metal film, siliciding the gate electrode, source and drain regions, and removing all unreacted metal film, forming an interlayer insulating film over the entire surface and contacting the interlayer insulating film. A method for manufacturing an MO8 type transistor, including the steps of forming a hole and forming a wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17624083A JPS6068655A (en) | 1983-09-26 | 1983-09-26 | Manufacture of mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17624083A JPS6068655A (en) | 1983-09-26 | 1983-09-26 | Manufacture of mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6068655A true JPS6068655A (en) | 1985-04-19 |
Family
ID=16010085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17624083A Pending JPS6068655A (en) | 1983-09-26 | 1983-09-26 | Manufacture of mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6068655A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109762A (en) * | 1991-05-16 | 1993-04-30 | Internatl Business Mach Corp <Ibm> | Semiconductor device and manufacture thereof |
| US6759315B1 (en) * | 1999-01-04 | 2004-07-06 | International Business Machines Corporation | Method for selective trimming of gate structures and apparatus formed thereby |
| CN102752991A (en) * | 2011-04-18 | 2012-10-24 | 索尼计算机娱乐公司 | Heat sink and electronic apparatus including heat sink |
| US9756761B2 (en) | 2011-04-18 | 2017-09-05 | Sony Corporation | Electronic apparatus |
-
1983
- 1983-09-26 JP JP17624083A patent/JPS6068655A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109762A (en) * | 1991-05-16 | 1993-04-30 | Internatl Business Mach Corp <Ibm> | Semiconductor device and manufacture thereof |
| US6759315B1 (en) * | 1999-01-04 | 2004-07-06 | International Business Machines Corporation | Method for selective trimming of gate structures and apparatus formed thereby |
| CN102752991A (en) * | 2011-04-18 | 2012-10-24 | 索尼计算机娱乐公司 | Heat sink and electronic apparatus including heat sink |
| US9756761B2 (en) | 2011-04-18 | 2017-09-05 | Sony Corporation | Electronic apparatus |
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