JPS63249246A - Memory system - Google Patents

Abstract

PURPOSE:To surely protect the contents of a memory at the time of ON or OFF of a power source or at the time of instantaneous stop of the power source by inhibiting the operation of a decoder for selecting the memory by a threshold circuit during the transient period of voltage at the time of ON/OFF of the power source to prevent the memory from being selected. CONSTITUTION:During the transient period of a power supply voltage, a reset IC 4 turns the voltage of an enable G 1 terminal in a decoder 3 to 'L' to inhibit the decoder 3 from selecting the memory 1, and during the inhibition, a 'H' signal is inputted to a chip selecting terminal S in the memory 1 by a backup power source to inhibit the writing and reading operation in/from the memory 1. Only when the 'H' signal is inputted to the enable G 1 terminal in the decoder 3, the writing and reading operation in/from the memory 1 can be executed. Consequently, the contents of the memory 1 can be protected.

Description

[Detailed description of the invention] [Industrial application field] TECHNICAL FIELD This invention relates to memory systems.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional memory system.

In the memory system shown in FIG. 3, a CMOS static RAM M5M5117P manufactured by Mitsubishi Electric Corporation is used as an example of the memory. As shown in the figure, memory 1 is connected to the CPU (central processing unit) and address bus AO to memory 2.
A10. Data buses DQ1 to DQ8 are connected,
The memory 1 also includes output enable OE and write enable WE terminals, which are control inputs from the CPU 2 to the memory 1, and a chip select S terminal, which is an output from the decoder 3. Dio-)'Di
A power source consisting of a power backup circuit combining ~D3 and a capacitor C is connected to the power supply voltage VCC terminal of the memory 1, and the power source is connected to the chip select S terminal of the memory 1 through a resistor R.

Figure 4 shows how the power is turned on in the memory system shown in Figure 3.
It is a figure which shows the time chart of the voltage at the time of @OFF.

Next, the operation of the above conventional memory system will be explained. When the power is off, when a backup power source is in use during a power outage, or when the CPU 2 is not accessing the memory 1, the power supply voltage of the memory 1 is V. rHJ is input to each terminal of C and chip select S, so that the memory 1 enters a standby mode, and write and read operations are prohibited. On the other hand, when the CPU 2 accesses the memory 1, the chip select S terminal of the memory 1 is set to rLJ, thereby writing the memo IJ 1.

The read mode is entered, and the memory 1 is operated by inputs from the CPU 2 to the output enable OE and write enable WE terminals, which are control inputs to the memory 1, and the memory 1 performs write and read operations.

[Problem that the invention seeks to solve]

In the conventional memory system as described above, as shown in FIG. 4, it takes a certain amount of time for the voltage applied to the CPU 2 to reach a steady state after 08:00 or when the power is turned off. In other words, the operation of the CPU 2 is not guaranteed below a certain voltage vt (voltage at time Tt - T*), and the voltage transition period (time T,
~T□, T, ~T.

period), the operation becomes unstable and stable, and the contents of memory 1 may be rewritten.
There were problems such as the need for two terminals. This invention was made to solve these problems, and the contents of the memory are The purpose is to obtain a memory system that does not destroy the memory.

[Means for solving problems]

A memory system according to the present invention includes a threshold circuit,
This threshold circuit inhibits the operation of the decoder that selects the memory during the voltage transition period when the power supply is turned on and off, thereby preventing the memory from being selected.

[Effect]

In the memory system of this invention, the threshold circuit is
When the CPU operation becomes unstable during the transition period of 1 voltage when the power is turned on and off, the enable input of the decoder for selecting the memory is set to rLJ to prohibit the memory from being selected and the voltage is When stable, the enable input of the decoder is brought to rHJ to allow the memory to be selected.

〔Example〕

FIG. 1 is a block diagram showing a memory system according to an embodiment of the present invention. The same or equivalent parts as in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted. 1st
The figure shows a memory system with a one-source backup circuit, and a reset I which is one of the threshold circuits as a protection circuit.
C4 is provided. Here, reset IC4 is I! An example of using a reset IC for power supply voltage detection and delay type system is shown.

Figure 2 shows the 0N power supply in the memory system in Figure 1.
11 is a diagram illustrating a time chart of voltage when OFF and a time chart of a signal outputted from the reset IC to the decoder correspondingly. FIG.

Next, the operation of the memory system which is one embodiment of the present invention will be described. Reset I used here
As shown in the second factor, C4' does not operate below the voltage VL, but always operates at r from 1 voltage vL to the voltage vH.
LJ is output, and rHJ is output after time td seconds from the time when the voltage exceeds V□. Such a reset I
Due to the characteristics of C4, when the voltage at 08 o'clock of the power supply is less than the voltage vL, the voltage at the enable G1 terminal of the decoder 3 is the same as the change in the power supply voltage, and then from the voltage VL to the voltage vH becomes rLJ, and After a time td seconds after the voltage vH is exceeded, the voltage becomes rHJ. When the power supply stops momentarily and its voltage becomes lower than voltage vH, reset IC4 always sets the voltage at the enable G1 terminal of decoder 3 to rLJ, and keeps the voltage V
When it rises above H, it becomes rHJ after time td seconds. Further, when the power is turned off, when the power supply voltage becomes less than the voltage vH, the voltage at the enable G1 terminal of the decoder 3 is set to rLJ, and when it becomes less than the voltage vL, the change is the same as the change in the power supply voltage.

In other words, when the power supply voltage is in a transition period, the reset IC4
sets the voltage at the enable G1 terminal of decoder 3 to rLJ, prohibits decoder 3 from selecting memory 1,
During that time, rHJ is inputted to the chip select S terminal of the memory 1 by the backup power supply, so that writing and reading operations cannot be performed. Writing and reading operations to memory 1 are enabled by enable G1 of decoder 3.
This is only when rHJ is input to the terminal of , and thereby the contents of memory 1 are protected.

〔Effect of the invention〕

As explained above, this invention provides a threshold circuit in a memory system, and uses this threshold circuit to
The structure prohibits the operation of the decoder that selects the memory during the voltage transition period at eOFF, preventing the memory from being selected, so it can be used as a dark value circuit using existing ICs.
It is said that it is possible to construct a memory system that can be configured using a memory card, etc., which does not make the circuit configuration complicated and inexpensive, and which can securely protect the contents of the memory even when the power is turned off at 8 o'clock or when the power is turned off, or when the power is momentarily stopped. It has excellent effects.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a memory system according to an embodiment of the present invention, and FIG. 2 is a time chart of voltage when the power supply is turned on and off in the memory system of FIG.
A diagram showing a time chart of a signal that the reset IC outputs to a decoder in response to this, FIG. 3 is a block diagram showing a conventional memory system, and FIG. 4 is a diagram showing the memory system of FIG.
FIG. 2 is a diagram showing a time chart of voltage when power is turned on and off in the system. In the figure, 1...Memory, 2...CPU (Central Processing Unit), 3...Decoder, 4...Reset IC (
threshold circuit). In each figure, the same reference numerals indicate the same or complementary parts.

Claims (2)

[Claims] (1) A CPU, a decoder and memory connected to the CPU, and a threshold circuit connected to a common power supply with the CPU, decoder, and memory, and whose level is inverted depending on whether the input voltage is equal to or higher than a predetermined threshold. In preparation, turn on/off the above power supply.
A memory system characterized in that the memory is in a write and read prohibited state during a period when the power supply voltage does not reach a normal operating range, such as during FF. (2) The memory system according to claim 1, wherein the threshold circuit is configured with a reset IC.