JPS5864700A - Storage protecting circuit - Google Patents

Abstract

PURPOSE:To perform protection with low power consumption by supplying a power voltage to the storage element selection terminal of a CMOS memory through a resistance, and inputting a selection signal or an inverted signal from a microprocessor to the selection terminal through a transistor (TR) inverter. CONSTITUTION:The output voltage 104 of a switching circuit 5 is supplied to the storage element selection terminal 106 of a CMOS memory 7 through a resistance 28. The collector of a TR27 is connected to the selection terminal 106, the emitter is connected to the output of an excessively low voltage detecting circuit 104, and a signal obtained by inverting the signal 105 of a microprocessor 1 through an inverting circuit 26 is inputted to the base. When a main power source 2 is turned off or in trouble, the TR27 turns off to supply the output 102 of a backup power source 3 through a switching circuit 5. This voltage is supplied to the power terminal Vcc of the CMOS memory 7 as well to inhibit storage holding, and writing and reading operation. Consequently, only small electric power is required for the storage protection during a break of the main power source.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection circuit for the contents of a complementary 11MO8 storage element (hereinafter referred to as a CMOS memory) when power is cut off or an abnormality occurs.

Conventionally, when a CMOS memory is used as a storage element in an electronic computer, a Q configured as shown in FIG. 1, for example, is common. That is, the microprocessor circuit 1 and the CMOS memory 7 are connected by a data bus, an address bus, a write/read signal (R/W signal) line, etc.
It is given to the storage element selection terminal of the OS memory 7. When the selection terminal lO6 is at a high level, read/write is prohibited, and when it is at a low level, a write/read operation is performed according to the data bus, address bus, R/W signal, etc. The operating voltage for the CMOS memory 7 is supplied by inputting the output 101 of the main power supply 2 to the switching circuit 6 and connecting the output line 104 of the switching circuit 6 to the power supply terminal Vj- of the storage device 7.

The voltage of the main power supply 2 is, for example, about 6V.

On the other hand, the undervoltage detection circuit 4 detects the output voltage of the main power supply 2, and sets the output l1110B to a high level when the output voltage is below a certain value. Since the output line 108 is connected to one input of the OR circuit 6, when the output line 108 becomes high level, the output line 108 is connected to the memory element selection terminal 10 via the OR circuit 6.
6 to high level to prohibit writing and reading. When the main power supply 2 is turned off, the power supply switching circuit 6 selectively outputs the output 102 of the backup power supply 8, so that a low voltage of about 2 to 8 V, for example, is supplied to the line 104 from the backup power supply 8. The CMOS memory 7, the undervoltage detection circuit 4. A low voltage from the backup power supply 8 is supplied to the OR circuit 6 and the like. The CMOS memory 7 can retain its stored contents even with a low voltage of 2 to 8 V, and the OR circuit 6 is also composed of 0MO8 and can operate at a low voltage, so writing and reading to the memory element 7 is prohibited. can do. As a result, the memory contents of the +II element 7 are protected 2. When the main power supply 2 is turned on, the output 108 of the voltage detection circuit 4 is at a low level, and the O storage element selection signal 1025 is sent from the microprocessor 1 to the OR circuit 6. However, in the conventional configuration described above, since the OR circuit 6 is composed of 0MO8, there is a drawback that the signal delay time is large. Also, 1. The power consumption of the OR circuit 6 is large. If the OR circuit 6 is configured with TTL, for example, in order to reduce the signal delay time, it cannot operate at a low voltage (2 to 8) when switched to the backup power supply 8. Increasing the voltage of the backup power supply 8 is not preferable because power consumption during backup increases. Since recent CMOS memories can be read and written at high speed, the above signal delay becomes a problem.

Also low voltage.

The above-described conventional configuration poses a problem in order to maintain memory with a low current.

FIG. 2 is a Thai chart showing voltages or signal waveforms at various parts of the conventional example shown in FIG. That is, when the main power source 2 is turned on, the voltage increases by, for example, 6 VK, and when the main power source 2 is turned off, the voltage becomes zero. The figure (b) shows the output 102 of the backup power supply 8, which is a constant voltage of, for example, 2 to 8 vst. (6) in the figure shows the output 104 of the power supply switching circuit 6. Before the main power is turned on, the output 102 of the backup power supply is output, and when the main power is turned on, the output 102 of the backup power supply is output.
The voltage is the same as that of the output 101, and (d) in the same figure shows the output 10B of the undervoltage detection circuit 4. Before the main power is turned on, the voltage is at the same high level as the output 102 of the backup power supply i18, and when the main power is turned on, Thereafter, it becomes a no-repel level equal to the voltage of the output 104 which increases as the output 101 of the main power supply 2 rises, but when the output 101 reaches a predetermined voltage or higher, it becomes a low level. FIG. 4(e) shows the storage element selection signal 106 of the microprocessor 1 input to the OR circuit 6, and the microprocessor 1 selects the data/x and address/<x in synchronization with the low level of this signal.

Send a signal to the R/W signal line, etc., and connect the CMOS memo IJ7.
send to The figure ('f) is the output of the OR circuit 6.

In other words, it is the voltage waveform of the memory element selection terminal 106, and has a waveform delayed from the selection signal 105 shown in FIG. The CMOS memory 7 is the selected fullA child 10.
Since the write/read operation is performed in accordance with the data on the data bus, address bus, etc. and the R/W signal when the e-color level is reached, the write/read operation is delayed by the delay time of the OR circuit 6. In other words, it can be seen that writing and reading operations cannot be performed at high speed.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and to
An object of the present invention is to provide a memory protection circuit that enables high-speed operation of a memory and protects the memory contents during non-operation with low power consumption.

The memory protection circuit of the present invention has a main power supply that supplies power while the memory element is in operation, a backup power supply that supplies power for memory retention, etc. when the memory element is not in operation, and a backup power supply that switches between the two power supplies to protect the memory element, etc. and an undervoltage detection circuit that detects the output voltage of the main power supply and outputs it when the output voltage is below a certain value, and when the main power supply is cut off, the backup power supply connects to the power supply terminal of the storage element and the memory. In a memory protection circuit that protects memory contents and prohibits reading and writing by supplying a voltage to an element selection terminal,
A microprocessor, comprising a resistor connecting the output of the power supply switching circuit and the storage element selection terminal, and a transistor having a collector connected to the storage element selection terminal and an emitter connected to the output of the undervoltage detection circuit. The memory element selection signal or its inverted signal is connected to the base of the transistor.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 8 is a circuit diagram showing one embodiment of the present invention. In this embodiment, the output 104 of the switching circuit 5 is connected to the storage element selection terminal 106 of the CMOS memory 7 through a resistor 28.
voltage is given. The collector of the transistor 27 is connected to the storage element selection terminal 106, and the emitter is connected to the output of the undervoltage detection circuit 4. At the base of the transistor 27, a signal obtained by inverting the storage element selection signal 105 from the microprocessor 1 by an inverting circuit 26 is inputted. The rest of the structure is the same as that of the conventional example shown in Fig. 1, and the same reference numerals as '' used in Fig. 1 indicate the same elements.Next, the operation of this embodiment will be explained. do. When the main power supply 2 is not turned on, the undervoltage detection circuit 4 outputs a high level, and the emitter of the transistor 27 is at a high level, so the transistor 27 is in an off state. Therefore, the output 102 of the backup power supply 8 is passed through the switching circuit 5, and a high level is applied from the output 104 of the switching circuit 5 to the storage element selection terminal 106 via the resistor 28.
゜The voltage from the output 104 is also applied to the power supply terminal v0. The above voltage is a low voltage of, for example, 2 to 8 volts outputted by the backup power supply 8, and the CMOS memory 7 is inhibited from retaining memory and writing/reading by the voltage, thereby protecting the stored contents. The power consumption of the CMOS memory 7 in this state is small, and the transistor 27 does not consume power. In other words, the power required to protect the memory when the main power supply 2 is turned off is very small, about 9 feet.
It has the effect of Further, at this time, the inverting circuit 26 can also be a circuit that does not consume power (however, at this time, it is not necessary that the inverting circuit 26 operates reliably).

Next, when the main power supply 2 is turned on, the output 101 rises and reaches a constant voltage as shown in Figure 4 (4).The output 102 of the park power supply 8 is as shown in Figure 4 (b) K. It is a constant value (2 to 8 melts).

The output 104 of the switching circuit 6 is switched from the voltage of the output 102 of the backup power supply 8 to the voltage of the output 101 of the main power supply, and reaches a constant voltage, as shown in FIG. 4(e). The output 108 of the undervoltage detection circuit 4 rises as the output 104 rises, as shown in FIG. ).

Since the output of the undervoltage detection circuit 4 becomes low level, the emitter of the transistor 27 shown in FIG. 8 becomes low level, so that the transistor 27 can operate as an inverter. , when the microprocessor 1 outputs the storage element selection signal 105 as shown in FIG. 4(), and the inverted signal 206 as shown in FIG. 1
A waveform as shown in (-) in the figure is input to 06. This waveform is the same as the storage element selection signal output from the microprocessor 1, and the delay time is extremely small.

This is because the signal delay time of the transistor 27 is much smaller than the delay time of the OR circuit 6 of FIG. 1, which is constructed of 0MO8. Further, if the storage element selection signal itself outputted from the microprocessor 1 is configured to have a reverse polarity, the inverting circuit 26 is unnecessary. This embodiment has the effect of enabling high-speed writing and reading of the 0MO8 memory 7. In addition,
Although the case where there is one CMOS memory 7 has been described above, storage line maintenance can be performed with a similar configuration for a plurality of memories.

As described above, in the present invention, a power supply voltage is supplied through a resistor to a storage element selection terminal of a CMOS memory, and a storage element selection terminal from a microprocessor is supplied to the selection terminal via an inverter configured with a transistor. The transistor is connected to input a signal or its inverted signal, and is configured so that it operates as an inverter when the main power is turned on and turns off when the main power is turned off, so that the memory contents can be maintained when the main power is turned off. - requires extremely little electric power, and can be read and written at high speed when the main power is turned on.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram including a partial block diagram showing an example of a conventional memory storage circuit, FIG. 2 is a time chart showing voltages or signals at various parts of the conventional example, and FIG. 8 is a circuit diagram of the present invention. A circuit diagram including a partial block diagram showing an embodiment of the fourth embodiment.
The figure is a time chart showing the voltages or signals of the main parts of the above embodiment. In the figure, 1... microprocessor, 2... main power supply, 8... backup power supply, 4... undervoltage detection circuit, 6... power supply switching circuit, 6... OR circuit, 7
... CMOS memory, 26... Inversion circuit, 27...
・, transistor, 28...resistance. Figure 1 Figure 2 (f) Figure 3

Claims (1)

[Claims] A main power supply that supplies power when the memory element is in operation, a backup power supply that supplies rounding power for memory retention, etc. when the memory element is not in operation, and a power supply switching circuit that switches between the two power supplies and connects them to the memory element, etc.; an undervoltage detection circuit that detects the output voltage of the main power source and outputs the output voltage when the output voltage is below a certain value, and supplies voltage from the backup power source to the power supply terminal and the memory element selection terminal of the memory element when the main power source is cut off. to protect the memory contents and prohibit reading and writing.
The overvoltage memory protection circuit includes a resistor connecting the output of the power supply switching circuit and the memory element selection terminal, and a nine transistor having a collector connected to the memory element selection terminal and an emitter connected to the output of the undervoltage detection circuit. 1. A memory protection circuit comprising: a microprocessor, and a memory protection signal or an inverted signal thereof from a microprocessor is connected to a base of the transistor.