JPH03256108A - Reset circuit for digital system - Google Patents

Abstract

PURPOSE:To prevent the generation of runaway in a microprocessor or miswriting in a memory by connecting a voltage monitoring IC with a a low operation power supply voltage to the output of the other voltage monitoring IC so that these ICs are used for resetting the microprocessor and turning on/off a power supply for the memory. CONSTITUTION:The voltage monitoring IC 1 is connected to the output of the voltage monitoring IC 2 with the low operation power supply voltage, the node between both the ICs 1, 2 is connected to the reset terminal of the microprocessor 3, a reset line L6 inputted to the chip select (CS) terminals of respective memories 5, a decoding circuit 4 for decoding an address bus L9, and the output lines L8 of the circuit 4 are connected to the other CS terminals of respective memories 5, and the micropocessor 3 and the memories 5 are connected to a data bus L7. When the operation of the IC 1 exceeds the operable voltage point (a) of the processor at the rise of the power supply, a reset signal is outputted. The reset signal is outputted before the IC 2 arrives at the point (a). Thereby, an OR logic between the outputs of the ICs 1, 2 is outputted to the line L6. Since the IC 1 is reset before the operation of the microprocessor 3, the microprocessor 3 can be prevented from generating runaway.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset circuit for a digital system, and particularly to a circuit suitable for turning on and turning off the power of a microcomputer system.

[Conventional technology]

The conventional device was published in Transistor Engineering, December 989 issue P
As described in Nos. 428 to 430, a reset circuit of a digital system was constituted by one reset generation circuit.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the operation of the reset generation circuit at a low voltage level when the power is turned on or turned off, and if the minimum operating voltage is high, the digital system will operate and the microprocessor will run out of control because it has not yet been reset. There was a problem.

An object of the present invention is to input a reset signal to the microprocessor before the microprocessor starts operating, thereby preventing the microprocessor from running out of control and further preventing erroneous data from being written to the memory.

[Means to solve the problem]

In order to achieve the second object, the present invention provides a voltage monitoring IC which is a reset generation circuit with a low minimum operating power supply voltage.

Also, to prevent the microprocessor from running out of control,
The outputs of a voltage monitoring IC with a low operating power supply voltage and a voltage monitoring IC with a high operating power supply voltage are connected and input to the reset of the microprocessor.

Furthermore, the present invention uses the output of a voltage monitoring IC with a low operating power supply voltage to turn on and off the power to the memory, thereby preventing writing of erroneous data to the memory.

[Effect]

A voltage monitoring IC with a low operating power supply voltage can obtain a reset output immediately after the power is turned on, before the digital system starts operating, and the reset output resets the digital system or microprocessor, allowing the digital system to operate normally. After reaching the voltage, release the reset. In addition, when the power is cut off, if the voltage reaches such a level that the digital system cannot operate normally, a reset output is output and the digital system is operated to be reset. As a result, the uncertain operating range of the digital system at power-on and power-off is reliably reset, so that malfunctions will not occur.

〔Example〕

FIG. 1 shows an embodiment of the reset circuit of the present invention, in which a voltage monitoring ICI and a voltage monitoring I with a low operating power supply voltage are shown.
The output of C2 is connected and inputted to the reset of the microprocessor 3, and the reset line L6 inputted to the chip select of the memory 5, and the decode circuit 4 which decodes the address bus L9 and its decode output L8 are input to the chip select of the memory. The microprocessor 3 and memory 5 are connected via a data bus L7.

FIG. 3 shows the reset timing of the circuit of FIG. 1. When the power supply voltage rises, the voltage monitoring ICI operates. After the voltage exceeds the microprocessor's operable voltage point (2), a reset signal is output. The voltage monitoring IC 2 with a low operating power supply voltage outputs a reset signal before reaching the 0 point. As a result, the reset line L6 becomes an OR logic of the outputs of the voltage monitors C1 and C2.

According to this embodiment, the microprocessor is reset before it starts operating, which has the effect of preventing the microprocessor from running out of control.

FIG. 2 shows an embodiment of the reset circuit of the present invention, in which the output of the voltage monitoring ICI is connected to the reset input terminal of the microprocessor 3, and the output of the voltage monitoring IC 2 is used to turn on and off the power of the memory 5. It is used for

FIG. 4 shows the reset timing of the circuit of FIG. 2. When the power supply voltage rises, the operation of the voltage monitoring IC 1 is such that a reset signal is output after the voltage exceeds the operating voltage point (2) of the microprocessor. The voltage monitoring IC 2 with a low operating power supply voltage outputs a reset signal before reaching the 0 point. As a result, the microprocessor may exceed the ■ point and run out of control until the reset reaches Lota, but the voltage monitoring IC
Due to the reset in step 2, power is not supplied to the memory in the operating area of the microprocessor before the reset, so no erroneous data is written. When the reset of the voltage monitor C2 is released, the microprocessor already has a reset input, so there is no runaway of the microprocessor.

In addition, when the power is cut off, after the microprocessor is reset by the power supply voltage monitoring ICI, a rise exceeding 0 point occurs, but since the power to the memory is not supplied due to the reset of the voltage monitoring IC2, the memory is affected by the runaway of the microprocessor. Writing of incorrect data will not occur.

Further, the decode output L8 after address decoding constitutes an AND logic circuit with the reset output of the voltage monitor C1, and its output is connected to the chip select and write enable terminals of the memory. As a result, a reset of the voltage monitoring IC1 due to a voltage drop is output, and writing to the memory is prohibited when a reset of the voltage monitoring IC2 is not output.

Therefore, it is possible to prevent erroneous data from being written to the memory due to external noise when the microprocessor is in a reset state and the bus is at high impedance. Furthermore, sufficient access time can be ensured for a memory or the like that requires a long access time after power supply.

Furthermore, in Figure 2, the power to the memory is turned on and off by the output of the voltage monitoring IC2, but the same effect can be obtained by controlling this with the memory control signal, such as chip enable or write enable. It will be done.

〔Effect of the invention〕

According to the present invention, since the digital system can be reset with a low voltage, malfunctions at the rise and fall of the power supply voltage can be prevented. In addition, voltage monitoring I with low operating voltage
By preventing memory writing with the reset output of C, malfunctions of the microprocessor after being reset can be prevented.

[Brief explanation of drawings]

1 and 2 are block diagrams of one embodiment of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention.
FIG. 4 is an explanatory diagram of the reset timing of FIG. 2, and FIG. 4 is an explanatory diagram of the reset timing of FIG. 2. 1... Voltage monitoring ICI, 2... Voltage monitoring IC2, 3...
・Microprocessor, 4...Decoding circuit, 5...
・Memory, L6...Reset signal, L7...Data bus, 7

Claims (1)

[Scope of Claims] 1. A reset generation circuit including an electrical detection means and a reset signal generation means that generates a reset signal based on the output of the voltage detection means, and a digital IC that is brought into an initial state by the output of the reset generation circuit. A reset circuit for a digital system, characterized in that a plurality of at least one of the voltage detection means and the reset signal generation means is provided in the digital system. 2. The reset circuit for a digital system according to claim 1, wherein the plurality of voltage detecting means detect different voltages. 3. The reset circuit for a digital system according to claim 1, wherein the reset signals of the plurality of reset signal generating means have different pulse widths. 4. The reset circuit for a digital system according to claim 1, wherein a plurality of said reset generation circuits have different operating power supply voltages.