JPS5847599Y2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device that can reliably hold data stored in a volatile semiconductor memory.

Conventional Volatile Semiconductor Memo IJ O) When retaining stored data, for example, a regular power supply and an emergency power supply are connected to the power supply line in parallel through a backflow prevention diode, and even in the event of a power outage, power is supplied from the emergency power supply and stored. I am trying to retain the data.

However, in such a device, the power supply voltage during operation of the semiconductor memory must be made higher to take into account the voltage drop in the reverse current prevention diode, and a separate power supply must be provided.

Further, when the regular power supply or the emergency power supply Q is turned off, a Φ transient voltage may mix into the write signal of the semiconductor memory and change the stored data.

Furthermore, when such a semiconductor memory Φ card is removed from the busbar or stored outside, the stored data may change due to an external signal, resulting in poor reliability.

The present invention has been devised in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device that has a simple configuration and can reliably retain data stored in a semiconductor memory.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG.

In the figure, reference numeral 1 denotes a first voltage detection circuit which opens a first switch 4 when the voltage vCC between power supply terminals 2 and 3 becomes lower than a predetermined voltage E1.

A second voltage detection circuit 5 opens a 20th switch 6 when the power supply voltage CC becomes lower than a predetermined voltage E2.

A semiconductor memory 7 stores data at an address accessed via an address line (not shown) or reads stored data.

And the power supply terminal of this semiconductor memory 7? a and 7b are connected between the power supply terminals 2 and 3 via the first switch 4.

Further, the semiconductor memory 70) power supply terminals 7a, 7
An emergency power supply 8 (voltage VsO of a battery, etc.) is connected to b via a backflow prevention diode 9.

On the other hand, an element 10 whose two-terminal voltage-current characteristic exhibits a knee voltage characteristic is inserted in series with the second switch 6, and the power supply terminal 2
, 3, and the connection point between the switch 6 and the element 10 is connected to the chip input terminal 8c of the semiconductor memory through the gate 11.
are connected via.

Note that for the power supply voltage VCC, the first. Second voltage detection circuit 1, 50) Operating voltage E1+E2 is set to satisfy the following equation.

Vcc) E2 > El With such a configuration, when the power supply voltage vCC is applied to the power supply terminals 2 and 3 from a common power supply (not shown), the first. The second voltage detection circuits 1 and 5 detect the first voltage. Second (7th
, 1 switches 4 and 6 are respectively turned on.

Therefore, the semiconductor memory 7 is supplied with current from the power supply terminals 2 and 3 via the first switch 4.

In addition, the voltage Vs of the emergency power supply 8 is set to the above-mentioned regular power supply voltage VC.
By setting the value lower than C, the diode 9 becomes reverse biased and turns off.

Then, when the second switch 6 is turned on, the voltage at the chip enable terminal 8c is raised to approximately cc, and the semiconductor memory 7 is enabled.

In this case, the knee% element 10 is located at point P in the characteristic diagram shown in FIG. 2, that is, at a flat operating point.

Then the mains voltage is cut off.

As shown in FIG. 3a, the voltage vCC drops to O.

In this case, when the voltage drops to E2, the second switch 6
is turned off, and the operating point of the element 10 shifts to Q in the characteristic diagram of FIG. 2, thereby setting the chip enable terminal 8c at a common potential as shown in FIG.

In other words, in such a semiconductor memory, by lowering the potential of the chip enable terminal to a non-enabled state, the card can be removed from or removed from the bus bar, induced by an external signal during storage, or switched from a regular power supply to an emergency power supply. Memory contents can be stably retained.

On the other hand, as shown in FIG. 2, in the knee characteristic element 10, when the power supply voltage Vcc decreases to a certain extent, the current rapidly decreases as well.

At point Q shown in FIG. 2, II/JE1 of the element 10, that is, the current change with respect to the applied voltage is extremely large.

Therefore, in this state, the dynamic resistance of the element 10 is small and the chip enable terminal 8c is connected to the common potential via a small resistance value.

Therefore, the chip enable terminal 8c can be reliably held in the non-enabled state, thereby reliably protecting the stored data.

When the voltage further decreases to El, the first switch 4 is turned off, the diode 9 is turned on, and the third switch 4 is turned off.
As shown in FIG. C, a voltage Vs is supplied to the semiconductor memory 7 from the emergency power supply 8.

In this state, the stored data is retained, but the data cannot be written.
Of course, it cannot be read.

Then, when the regular power is supplied again, the first switch 4 is turned on, and then the second switch is turned on to enter the chip enable state.

Therefore, in a steady state, the voltage supplied to the semiconductor memory 7 does not decrease, and stored data can be reliably retained even when the regular power supply is turned off.

Further, when data is held by the emergency power source 8, the chip enable terminal can be set to a common potential due to the low resistance of the Knee characteristic, and there is no possibility that the stored data will be changed by noise or the like.

Furthermore, by using an element with the above Knee characteristic, power consumption is significantly lower than when a large current is passed through a low resistance to raise the voltage of the chip enable terminal 8c.

For example, by passing a current of 250 mA through a resistor of 21, the voltage becomes 5V.
If a field effect transistor is used as the element 10, only a few mA of current is consumed compared to obtaining a terminal voltage of .

As described in detail above, according to the present invention, it is possible to provide a semiconductor memory device that is simple in configuration and can reliably retain stored data with low power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a characteristic diagram of a knee characteristic element, and FIG. 3 is a graph showing the operation of the above embodiment. 1...First voltage detection circuit, 2, 3...
・Common power supply terminal, 4...First switch, 5.
...Second voltage detection circuit, 6...Second switch, 7...Semiconductor memory, 8...
・Emergency power supply, 9...Reverse current prevention diode.

Claims (1)

[Scope of utility model registration request] a semiconductor memory to which an operating voltage is applied from a normal power supply via a first switch; an emergency power supply having a lower voltage than the normal power supply to which the operating voltage is applied to the semiconductor memory via a backflow prevention diode; 10) a voltage detection circuit that turns off the first switch in response to a drop in power supply voltage; and a second switch inserted between the common power supply and the semiconductor memory IJ □) chip enable terminal; A knee characteristic element inserted between the chip enable terminal and the common potential, and a second switch that turns off the second switch in response to the drop in the common power supply voltage to zero prior to operation of the first voltage detection circuit. A semiconductor memory device comprising a voltage detection circuit.