KR890002549Y1 - Preservation circuit of record data - Google Patents
Preservation circuit of record data Download PDFInfo
- Publication number
- KR890002549Y1 KR890002549Y1 KR2019860009550U KR860009550U KR890002549Y1 KR 890002549 Y1 KR890002549 Y1 KR 890002549Y1 KR 2019860009550 U KR2019860009550 U KR 2019860009550U KR 860009550 U KR860009550 U KR 860009550U KR 890002549 Y1 KR890002549 Y1 KR 890002549Y1
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- KR
- South Korea
- Prior art keywords
- power supply
- transistor
- terminal
- ram
- memory device
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
- H02H11/006—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of too high or too low voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안에 따른 회로도이다.1 is a circuit diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 전원검출부 CPU : 중앙처리장치1: Power detector CPU: Central processing unit
RAM : 기억소자 TR1, TR2: 트랜지스터RAM: Memory element TR 1 , TR 2 : Transistor
R1-R6: 저항 D1: 다이오드R 1 -R 6 : Resistor D 1 : Diode
B : 백업용전원B: Power supply for backup
본 고안은 기억소자에 기억되어 있는 데이타의 보존회로에 관한 것으로, 특히 공급전원이 정상 동작전원의 범위에서 벗어나 불안정한 상태일 때에 기록된 데이타에 에러가 발생하지 않도록 한 기록데이타 보존회로에 관한 것이다.The present invention relates to a data preservation circuit stored in a memory device, and more particularly, to a write data preservation circuit in which an error does not occur in the recorded data when the supply power supply is out of the range of a normal operating power supply and is unstable.
종래의 경우에는 공급전원이 불안정한 상태에서도 데이타를 기억소자에 기록 또는 기억소자로부터 안출하였기 때문에 데이타에 에러가 발생하게 되고 이 에러 데이타를 그대로 사용함으로 전체 운용시스템에 더 큰 에러를 유발시켰으며 또한 전원이 일정치 이하로 떨어지거나 공급이 불시에 차단되게 되면 기억소자(RAM)의 내용이 소거되어 사용자가 처음부터 다시 해당 작업을 시작해야 되는 등의 단점이 있었다.In the conventional case, an error occurs in the data because the data is written to or written from the memory device even when the power supply is unstable, and the error data is used as it is, causing a larger error in the entire operating system. If this falls below a certain value or the supply is cut off inadvertently, the contents of the RAM are erased and the user has to start the work again from the beginning.
본 고안은 이와 같은 종래의 단점을 감안하여, 공급전원이 불안정한 상태일 때는 중앙처리장치 및 기억소자를 디스에이블(Disable)시켜 그의 동작을 중지시키고, 전원이 일정치 이하로 떨어지거나 공급이 불시에 차단되는 경우에는 백업(Backup) 전원을 인가해주므로써 기억소자의 기억내용이 소거되는 것을 방지하게 안출한 것으로 도면에 의하여 이를 상세히 설명하면 다음과 같다.In view of the above disadvantages, the present invention disables the central processing unit and the memory device when the power supply is unstable, and stops its operation. In the case of being cut off, the backup power is applied to prevent the memory contents of the memory device from being erased.
전원공급단자(DC)는 전원검출부(1)의 전원단자(Vc1), 전원감지단자(Sr) 및 콜렉터가 기억소자(RAM)의 전원단자(Vc2)에 접속된 트랜지스터(TR1)의 에미터에 접속하고, 전원감출부(1)의 출력측은 중앙처리장치(CPU)의 리세트단자에 접속함과 아울러 트랜지스터(TR1)(TR2)의 에미터 및 베이스에 각기 접속된 저항(R2)(R3)의 접속점에 접속하며, 트랜지스터(TR2)의 콜렉터는 트랜지스터(TR1)의 베이스 및 콜렉터에 저항(R5)(R6)을 각기 통해 접속함과 아울러 기억소자(RAM)의 인에이블단자에 접속하고 백업(Backup)용 전원(B)은 다이오드(D1)를 통해 상기 트랜지스터(TR1)의 콜렉터 및 기억소자(RAM)의 전원단자(Vc2)에 접속한 것으로 상기에서 전원검출부(1)는 전원 공급단자(DC)의 전원이 원공급전원 레벨보다 일정치 이하로 떨어지면 그것을 검출하여 저전위 신호를 출력하게 하였다.The power supply terminal DC includes a power supply terminal Vc 1 , a power detection terminal Sr, and a collector of the transistor TR 1 connected to the power supply terminal Vc 2 of the memory device RAM. Connected to the emitter, the output side of the power supply unit 1 is a reset terminal of the central processing unit (CPU) Access Also the addition of a transistor (TR 1) (TR 2) the emitter and and connected to the connection point of the resistance (R 2) (R 3) connected respectively to the base, the collector transistor (TR 1) of the transistor (TR 2) in the A resistor (R 5 ) (R 6 ) is connected to the base and the collector, respectively, and the enable terminal of the memory element (RAM). The backup power supply B is connected to the collector of the transistor TR 1 and the power supply terminal Vc 2 of the memory device RAM through a diode D 1 . 1) detects when the power of the power supply terminal (DC) falls below a certain level below the original supply power level, and outputs a low potential signal.
이와 같이 구성한 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured in this way as follows.
전원공급단자(DC)를 통해 공급전원이 정상적으로 인가되면 전원검출부(1)는 이를 감지하여 고전위 신호를 출력시키고, 이에 따라 트랜지스터(TR2)의 베이스에 고전위가 인가되므로 그가 온되며, 또한 트랜지스터(TR2)의 콜렉터에 접속된 트랜지스터(TR1)의 베이스는 저전위가 되어 그가 온되고, 이에 따라 전원공급단자(DC)의 전원이 트랜지스터(TR1)를 통해 기억소자(RAM)의 전원단자(Vc2)에 인가되며, 트랜지스터(TR2)의 콜렉터의 저전위가 기억소자(RAM)의 인에이블단자에 인가되어 기억소자(RAM)는 인에이블되어 중앙처리장치(CPU)와 상적인 동작을 수행하게 된다.When the power supply is normally applied through the power supply terminal (DC), the power detector 1 detects this and outputs a high potential signal. Accordingly, since the high potential is applied to the base of the transistor TR 2, it is turned on. The base of the transistor TR 1 connected to the collector of the transistor TR 2 becomes low potential and is turned on, so that the power supply of the power supply terminal DC passes through the transistor TR 1 of the memory device RAM. It is applied to the power supply terminal Vc 2 , and the low potential of the collector of the transistor TR 2 is the enable terminal of the memory element RAM. When applied to the memory device RAM, the memory device is enabled to perform normal operation with the CPU.
이와 같은 상태에서 전원공급단자(DC)의 전원레벨이 규정치보다 일정치 이하로 인가되면 상기한 바와 같이 전원검출부(1)는 이를 감지하여 저전위 신호를 출력시킨다.In this state, if the power level of the power supply terminal (DC) is applied to a predetermined value or less than the prescribed value as described above, the power detector 1 detects this and outputs a low potential signal.
이와 같이 출력된 저전위신호는 중앙처리장차(CPU)의 리세트단자에 인가되어 중앙처리장치를 리세트시키며, 또한 트랜지스터(TR2)의 베이스에 인가되어 그가 오프되고, 이에 따라 그 트랜지스터(TR2)의 콜렉터는 고전위가 되어 그 고전위가 기억소자(RAM)의 인에이블단자에 인가되므로 기억소자(RAM)는 상기와는 반대로 디스에이블(Disable)되어 잘못된 데이타로 기억되는 것을 방지하게 된다. 또한 전원공급단자(DC)의 전압이 차단되거나 강하하여 백업용전원(B) 전압이하로 떨어지면 백업용전원이 기억소자(RAM)의 전원단자(Vc2)에 인가되게 되어 기억소자(RAM)의 데이타를 보존할 수 있게 된다.The low potential signal output in this way is a reset terminal of the central processing unit (CPU). Is applied to reset the central processing unit, and is also applied to the base of the transistor TR 2 so that it is turned off, thereby causing the collector of the transistor TR 2 to become high potential and its high potential to be stored in the memory element RAM. Enable terminal of Since it is applied to the memory device (RAM) is in contrast to the above (Disable) to prevent from being stored as wrong data (Disable). In addition, when the voltage of the power supply terminal (DC) is cut off or drops and falls below the backup power supply (B) voltage, the backup power is applied to the power supply terminal (Vc 2 ) of the memory device (RAM), thereby storing the data of the memory device (RAM). I can save it.
이상에서 설명한 바와 같이 본 고안은 공급전원이 불안정하거나 차단되면 백업용전원을 인가함과 아울러 기억소자를 디스에이블시킴으로써 잘못된 데이타의 기록을 방지함은 물론 기억된 데이타가 소거되는 것을 방지하는 효과가 있는 것이다.As described above, the present invention has the effect of preventing the writing of wrong data as well as the erasing of stored data by applying a backup power supply and disabling the memory device when the power supply is unstable or cut off. .
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860009550U KR890002549Y1 (en) | 1986-07-03 | 1986-07-03 | Preservation circuit of record data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860009550U KR890002549Y1 (en) | 1986-07-03 | 1986-07-03 | Preservation circuit of record data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR880003467U KR880003467U (en) | 1988-04-13 |
| KR890002549Y1 true KR890002549Y1 (en) | 1989-04-29 |
Family
ID=19253337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019860009550U KR890002549Y1 (en) | 1986-07-03 | 1986-07-03 | Preservation circuit of record data |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR890002549Y1 (en) |
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1986
- 1986-07-03 KR KR2019860009550U patent/KR890002549Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR880003467U (en) | 1988-04-13 |
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