JPS6324724A - Encoding and decoding circuit - Google Patents

Abstract

PURPOSE:To contrive combination use of a hardware as an encoding circuit, and a decoding circuit, by multiplying the output of a syndrome calculation part by a prescribed constant stored in a memory in advance sequentially, taking the accumulated sum of the products, and obtaining the inspection symbol of a bit of input information as the accumulated sum. CONSTITUTION:The bit of input information is supplied to the syndrome calculation part 16, and the outputted terminal 3 of a calculated result can be output from the terminal to decode a syndrome value. Also, the syndrome value is inputted to the multiplication circuit 11 of a Galois body, and and the product of the constant read out from a first memory 12, is calculated, and the product is inputted to the adder 13 of the Galois body. The added result of the adder 13 is inputted to a second memory 14, and the stored content of the second memory 14 is supplied to the adder 13, and a sum of the multiplier 11 side is calculated. In other words, the accumulated sum of the output of the multiplier 11 can be found by the adder 13, and the second memory 14, and the content of the second memory 14 is supplied to register 15 which latches a calculated output, then, the inspection symbol is outputted from the output terminal 10 of the register.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit for encoding and decoding, and more specifically, a syndrome circuit used for decoding a signal that performs error correction, and an encoding circuit. We propose a new circuit that can also be used as a circuit.

[Prior art]

A circuit is known that functions as both a syndrome circuit used for decoding a signal to be subjected to error correction and a Chen circuit that calculates the coefficients of an error locator polynomial from the syndrome and specifically calculates the error position as the root of the error locator polynomial. ing. FIG. 2 shows a conventional example of a syndrome-chain combined circuit for a Reed-Solomon code with a minimum distance of 17 on a Galois field GF (2"). A received word of an 8-bit l symbol is input to input terminal 1. , through switch SX, and adder A0 . A,...A
8-bit registers Lo, L+, which are cleared in advance through 5WIS and S wt, which are switched to the terminal W side as shown in the figure.
- Sequentially given to L+s and latched here. Register LI, L.

...The latch contents of LIS are multipliers B+, Bz on Galois field GF (2')...
′) constant α on

Multiplied by α2...αI5, adders A, Az...
The sum is given to A + s, and the sum with the next human power from the input terminal 1 side is calculated, and the sum is given to registers L+, Lz...L+s
latched to. The latched contents of register L0 are directly added to the next manual input in adder A0, and the sum is added to register L.
Latched to 0. When all received words have been input, switch S. . 2 S□...5WI5 is switched to the terminal U side, and the calculated syndrome is sent to registers Lo, L+...
-L12 is sequentially shifted and sequentially output from the output terminal 3 provided on the register LIS side.

On the other hand, the function as a chain circuit is performed as follows. That is, the contents of each register Lo, L+ .
The sum of the contents of .

The Chen circuit uses an element α0 . of the Galois field GF (2B) as an indefinite term α-・・
・While detecting whether or not αass, a clock is input and the element is changed, and the solution to the error locator polynomial is calculated using the number of clocks when it is “0”. Such processing =o, 1...n-1 is repeated by the number of signs.

In the illustrated circuit, a clock is input while detecting whether or not the registers Lo, L+ . . . L8 have the respective coefficients σ, (σ., σ1 . By clock input, the output of register L+...L8 is multiplier circuit B+
, Bz...B8 are multiplied by α, α2...α8 and latched again into the registers Lo, L+...La. By repeating this process, Σσ, (αJi is
Calculations are performed sequentially from =0 to n-1.

[Problem to be solved by the invention 9 As described above, the decoding circuit can be made smaller by using both the hardware of the syndrome circuit and the Chen circuit. There was a problem in that the circuit was too large when combined with the integrated circuit.

The present invention was made to solve these problems, and provides an encoding/decoding system that can be miniaturized by being able to serve as an encoding circuit in addition to a syndrome circuit or a chain circuit. The purpose is to provide an integrated circuit.

[Means for solving problems]

The encoding/decoding circuit according to the present invention sequentially multiplies the output of the syndrome calculation unit by a required constant stored in advance in a memory, takes the out-of-phase of the product, and obtains a test symbol of human power information as this out-of-phase. This is what I did.

[Effect]

A provisional syndrome is calculated in the syndrome calculation section based on the information to be encoded. This calculated value is multiplied by a constant read from memory, the products are multiplied, and the resulting test symbol is obtained.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof. In FIG. 1, 1 is an input terminal of information to be encoded or information to be decoded, and the input information is given to the syndrome calculation section 16.

The syndrome calculating section 16 may also serve as a Chen circuit as shown in FIG. 2, or may only perform syndrome calculations. The syndrome calculation result output terminal 3 can output the syndrome value for decoding. Further, the syndrome value is input to a Galois field multiplication circuit 11, where a product with a constant read out from the first memory 12 is calculated, and the product is input to a Galois field adder 13.

The addition result of the adder 13 is input to the second memory 14.

The stored contents of the second memo January 4 are given to the adder 13, and the sum with the multiplier 11 side is calculated. In other words, whether the outputs of the multiplier 11 are out of phase between the adder 13 and the second memory 14 is determined.

The contents of the second memory 14 are applied to a register 15 that latches the calculation output, and a test symbol is output from its output terminal 10.

Next, the principles of the operations performed by these circuits will be explained first. The syndrome vector S of the received word vector r given to input terminal 1 is S = r H”
...fl). Here H is a parity check matrix and T indicates the transpose of that matrix.

On the other hand, the vector r of the received word is y = (y, : yc) = [Ti :Oc) + (Of :D.]...
・It can be expressed as (2). Here, r is an information symbol portion of vector T, T is a check symbol portion, and 0c and 0 each represent a zero vector.

If no error occurs, the syndrome calculation unit S is 5=vHT=0=・(31), so encoding can be said to be equivalent to calculating the vector Irc that satisfies equation (3). .

That is, f21. From formula (3), rH'=((Ding= :oc) + (Oi :y
c])H”=(yi :0c)H”+(Ot :y
c) H”=5z + (ot: dingゎ)H”=
O...(4), -, Si = (Oi: Tc)
H" ・15) H is given by the following equation (6). However, if d is the received vector [OL 2.], then the temporary syndrome S becomes Si-[Ol :Tc)HT. rc is Tc=A-'SL ・(81 However, the circuit shown in FIG. 1 is configured to calculate (8) 2. That is, when information is input, the syndrome calculation section A provisional syndrome S, is calculated. Elements α°, etc. of A −1 are stored in the first memo i month 2 in advance, and these elements are sequentially read out and the multiplication circuit 11
is multiplied by syndrome S, and input to the adder 13.

The second memory 14 is cleared in the initial state, and due to the action of this memo 4 and the adder 13, A-',
Each term of S is calculated and taken to have a different phase each time. Finally in register 15) Moxibustion symbol Ding. is latched, and this is output from the output terminal 10.

〔effect〕

Since the circuit of the present invention is constructed as described above, the hardware of the encoding circuit and the decoding circuit can be shared, and the circuit can be miniaturized. In addition, when using a syndrome calculation unit that also serves as a Chen circuit as shown in Figure 2,
Encoding and decoding circuits can be further miniaturized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit of the present invention for water removal, and FIG. 2 is a water release circuit diagram of a conventionally known syndrome-chen circuit. 11... Multiplication circuit 12... First memory 13...
Addition circuit 14...Second memory 16...Syndrome calculation unit Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Procedural amendment (voluntary) 3. Representative of the person making the amendment: Moriya Shiki 4, Agent address: 2-2-3-5, Marunouchi 2-chome, Chiyoda-ku, Tokyo, ``Detailed description of the invention'' column and drawing 6 of the specification subject to the amendment, Contents of the amendment 6-1 In the "Detailed Description of the Invention" column of the specification + 11, on page 2, line 10 of the specification, the word "adder" is corrected to "adder." (2) In the 8th line of page 3 of the specification, the phrase "performed." is corrected to "realized." (3) In the third line of the specification, lines 17-20, “The sum...
...(omitted)...The statement "by clock number" has been corrected. (4) On page 4, line 3 of the specification, between “In the circuit” and “Register”, “First, open switch SX and switch SwO~
Add "Switch Sw8 to U side". (5) On the 5th line of page 4 of the specification cylinder, replace the text ``Set'' with ``Set.'' Next, turn switch S and 1° to 5WII to W.
"Switch to the side," he corrected. (6) Add the following sentence to the end of page 4, line 12 of the specification section. “At this time, the outlet Σσ, (αJ) of output terminal 2 is “0”
``The input chronograph number indicates the root of the error locator polynomial.''+71 In the second line of page 8 of the specification, after ``However, d is'', ``is the design distance of the code.'' is added. . (8) The right side of A-1 on the fourth line from the bottom of page 8 of the specification is corrected as follows. 6-2 Figure 2 of the drawing is corrected as indicated in red in the attached drawing. 7. List of attached documents

Claims (1)

[Claims] 1. Multiplying a syndrome calculation unit that calculates a syndrome of input information, a first memory in which necessary constants are stored in advance, and the syndrome output by the syndrome calculation unit and the contents sequentially read from the first memory. The present invention includes a Galois field multiplication circuit, a second memory, and a Galois field addition circuit for adding the output of the multiplication circuit and the contents of the second memory, and obtains an input information test symbol in the second memory. Characteristic encoding/decoding circuit.