JPH03190326A - Polynomial generating circuit for error correction calculation - Google Patents

Abstract

PURPOSE:To decrease the number of multipliers for Galois field in use and to save the circuit scale by changing the selection of a 2-input 1-output selection circuit so as to execute the production of an error correction calculating polynomial in the erasure correction of a reed Solomon code. CONSTITUTION:First and 2nd selection circuits 130-138 and 140-148 are used to generate and calculate as 3 kinds of polynomials as syndrome polynomial, error location polynomial, and error evaluation polynomial and adders 110-118 and multipliers 120-128 for Galois field are used in common. Thus, the number of the multipliers 120-128 for Galois field is reduced, the circuit scale is reduced, and 2t+1 stages of arithmetic means comprising registers 100-108, Galois field adders 110-118, multipliers 120-128, and 1st and 2nd selection circuits 130-138, 140-148 are arranged and connected to execute the generation of polynomials at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a code error correction system for an information recording/reproducing apparatus [Prior art] In an information recording/reproducing apparatus, a code error correction system is used to improve reliability against data errors. - Error correction is performed using an error correction code such as Solomon code. As a method of error correction, there is an erasure correction method that uses error position information indicated by a pointer. This method is described in Japanese Unexamined Patent Application Publication No. 1332/1983, and is as follows.

The Reed-Solomon code decoding method is (1) Syndrome (polynomial) calculation (2) Derivation of error locator polynomial and error evaluation polynomial (3) Calculation of error position and error value (4) Execution of error correction It is executed in the following steps.

In the case of erasure correction (there is no error other than the error position indicated by the pointer), since the error position is known, in the case of erasure correction, decoding is executed in the following procedure.

(1) Calculation of syndrome (polynomial) and error locator polynomial (2) Derivation of error evaluation polynomial (3) Calculation of error value (4) Execution of error correction Parity generation polynomial for t-fold error correction of Reed-Solomon code〇 ( z) is shown below. Here α is the mth order (m=
Galois field GF (2”
), and multiplication and addition are performed on this Galois field.

G (z)=n (z+α1) Root α' of this error correction parity generation polynomial〇 (z)
(i=1.2..-, 2t) and the received signal Da.

I) fi-,, +++ Day Dt <code length n)
As a result, syndromes 80 to 5it-t shown below are generated.

Sag-L=D11 ・(z"""-"+D, -+#α
lt-In-17+,.

+D,・α +DI・α =ΣD,・α! t゛ll-11 is++t SJ=ΣD,・aC river) -fl-11m1 (O≦j (2t) s, == Yes, and they satisfy the following formula.

φ(z)・X2t+σ(z)・5(z)=ω(z) From this, the following equation holds true.

σ(z)・5(z)mit+>(z) (mod
z") However, 5(z): So+St'Z"""5it-L j
z" -1= Σ S+-z' -0 : Syndrome polynomial %) : Error locator polynomial ω (Z) = Σ El-IT (z-xk)・
iεE amεE, ak≠@i: error evaluation polynomial where E is an error, El is placed at the error position et)
The error value Xi is a value (error position information) corresponding to the error position 1ist as shown below.

x1= a−f@l−11[cr (xυ=O] The syndrome polynomial S (z) is a polynomial whose coefficient is the syndrome, and the error location polynomial σ(z) is a polynomial whose root is the error location information. Multiplying these two equations, x
The remainder after dividing by zt (the term less than 2 of the product polynomial) is
The error value is calculated as follows from the error locator polynomial 〇(Z) and the error evaluation polynomial ω(z), which are the error evaluation polynomial ω(Z).

(The error position is indicated by a pointer and is known.) To calculate the error value, σ' (2), which is obtained by formally differentiating the error position polynomial σ(z), is used. σ′ (2) is shown below.

(Hereinafter, blank space) =2t°σ2.・Zit−+ + (2t−1) ・σ2. −4・zIt−1+2・
σ2・2+σ1 = (7!t-, °21cm1+σmit-a, zIt
-4+...+σ3H22+σ, =Σσ□-1・Z! +4 xl (“, -2·α1=α1+α′=O: i is an arbitrary value) where σ is the coefficient of the i-th term of the error locator polynomial σ(z).

The error position information xt is expressed as the formal differential σ'(
z) and is substituted into the error evaluation polynomial ω(Z), the result is as follows.

σ (X,) = rI (X, -X,)6 to εE, ak≠6i ω(xt) =E+ ・n (xt xk)a
mεE, ak≠ai From these, the error value El at the error position e is determined as follows.

In the case of a Reed-Solomon code for heavy error correction, 2 syndromes are generated, and a maximum of 2 data can be corrected. Further, the degree of the error locator polynomial is at most 2t, and the degree of the error evaluation polynomial is at most 2t-1.

A conventional generation circuit for error correction calculation polynomials (syndrome polynomial/error locator polynomial/error evaluation polynomial) will be described below (in the case of t=4).

FIG. 2 is a block diagram showing a conventional syndrome polynomial generation circuit. In FIG. 2, 2°O to 207 are registers, 210 to 217 are Galois field adders, and 220 to 207 are Galois field adders.
227 is a Galois field multiplier. registers, adders,
and multipliers are connected in 8 stages, and each multiplier has roots α1 to α
9 is supplied. Receive data Dn+D from input terminal
a-L? ...D2. Dl is input to the first order, and the value in the register at the end of the input becomes the syndrome (coefficient of the syndrome polynomial).

FIG. 3 is a block diagram showing a conventional error locator polynomial generating circuit. In Figure 3, 300 to 308.310
317 are registers, 320 to 327 are Galois field adders, and 330 to 337 are Galois field multipliers. A unit configuration consisting of two registers, an adder, and a multiplier is connected in eight stages, and each multiplier is supplied with a value X□ to X corresponding to an error position indicated by a pointer. From the input terminal 1. By sequentially inputting O, O, . . . , σ8. σ7. ..., σ0. σ. are sequentially output (σi: coefficient of the i-th term of the error locator polynomial σ(z)).

FIG. 4 is a block diagram showing a conventional error evaluation polynomial generation circuit (polynomial multiplication circuit). In Figure 4, 4
00, 410 to 417 are registers, 421 to 427 are Galois field adders, and 430 to 437 are Galois field multipliers. Eight stages of unit configurations consisting of registers, adders, and multipliers are connected, and each multiplier has a syndrome 87
~S0 is -supplied. The coefficients σ, , σ7 . of the error locator polynomial are input from the input terminal. ... σ□, σ. are input sequentially, and the value of each register at the end of input becomes the coefficient of the error evaluation polynomial. Furthermore, by inputting O2... from the input terminal, the coefficient ω7. of the error evaluation polynomial is input from the output terminal. ω8
．． ..., ω1. ω. are output in j order.

[Problem to be solved by the invention]

However, if the polynomial generation circuit for error correction calculation is configured to consist of a syndrome polynomial generation circuit, an error locator polynomial generation circuit, and an error evaluation polynomial generation circuit as described above, a large number of Galois field multipliers will be used.
This has the problem that the circuit scale becomes large. For example, the scale of a Galois field GF (2”) multiplier is approximately 500
In the case of a Reed-Solomon code for heavy error correction, 6 multipliers are required, and this multiplier alone can handle 30
00.t gate, and as the correction capability increases, the circuit scale also increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a polynomial generation circuit for error correction calculations that can reduce the circuit scale without impairing the high speed of calculations.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention inputs input data and the root of an error correction parity generation polynomial or specific data, and selects and outputs one of the input data.
a selection circuit, a Galois field multiplier that multiplies the output from the first selection circuit and the output from the register and outputs the multiplication result, and inputs input data or specific data and output data, a second selection circuit that selects and outputs either one; a Galois field adder that adds the output from the second selection circuit and the output from the multiplier and outputs the addition result; an arithmetic means constituted by the register that temporarily stores the output from the adder and then outputs it;
Arranged in 2t+1 stages from top to bottom, the output of the register of each calculation means is input as the output data to the second selection circuit of the calculation means one stage lower, and the common data is input to each calculation. said first and second means;
The coefficients of each of the syndrome polynomial, error locator polynomial, and error evaluation polynomial are obtained from the output of the shifter of each menu means.

[Effect]

In the present invention, by using the first and second selection circuits, the Galois field adder and multiplier are used in common in the generation operation of three types of polynomials: syndrome polynomial, error locator polynomial, and error evaluation polynomial. are doing. As a result, the number of Galois field multipliers used can be reduced, and the circuit scale can be reduced.

Furthermore, by connecting the arithmetic means consisting of registers, Galois field adders, multipliers, and first and second selection circuits in 2t+1 stages, it is possible to perform polynomial generation operations at high speed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a polynomial (syndrome polynomial/error locator polynomial/error evaluation polynomial) generation circuit for error correction calculations as an embodiment of the present invention, in the case of a Reed-Solomon code for quadruple error correction. This shows that.

In FIG. 1, 100-108 are registers, 110-108 are registers, and 110-108 are registers.
118 is a Galois field adder, 120 to 128 is a Galois field multiplier, 130 to 138° 140 to 148 is a 2-man power 1
This is an output selection circuit.

Although the clock signal of the register is not shown,
Emitted for each input from the input terminal.

Further, α is a primitive element of the Galois field, and the parity generation polynomial for error correction (z) is given by the following equation.

G(z)=(z+α1)・(z+α2)・(Z+α3)
...(2+α7)・(2+αS) Hereinafter, the explanation will be made in the following order.

a) Generation of syndrome (polynomial)) Generation of error locator polynomial C) Generation of error evaluation polynomial 140 to 148 are selected as B. This results in a circuit similar to that shown in FIG. The multiplier has the output of the register and the root α' (i=1.
2. ...8) is supplied, and the adder is supplied with the output of the multiplier and the received data from the input terminal (adder 110
is supplied with 0).

Then, the output of this adder is inputted into the register again.

This operation is repeated for code length (n). The outputs of the registers 101 to 108 at the time when all received data have been input become syndromes (polynomial coefficients) S7 to S.

As an example, receive data D from the input terminal. -4゜・
The output of the register 101 when +DxtDx is input is shown below.

(Left below) a) Generation of syndrome (polynomial) First, as an initial setting, registers 100 to 108 are cleared, and two-man power one output selection circuits 130 to 138 degrees are fed, and the adder receives the output of the multiplier, The output of the register at the lower stage is supplied (O is supplied to the adder 108). Then, the output of this adder is input to a register. This operation is repeated for the number of pointers. The outputs of registers 100 to 108 at the time when all error position information has been input are coefficients σ, to σ corresponding to each term of the error position polynomial.

bawl.

For example, error position information X engineering, x2. The outputs of registers 100 to 108 when X is given are shown in polynomial expression.

(Hereinafter, blank space) b) Generation of error locator polynomial First, clear registers 100 to 107 as initial settings, input α0=1 to register 108, and perform two-manual 1-output selection circuits 130 to 138° and 140 to 148. Select A
shall be. The multiplier receives error position information (Xly X21 x3t ”'HX(
Coefficients ω7 to ω corresponding to each term of the product of the product of the supplied Drome polynomial 5(z) and the error locator polynomial σ(Z)). bawl.

As an example, the outputs of registers 101-108 when syndromes 87-S, (syndrome polynomial 5 (Z)), and error position information XxHXzyX3 are given are shown in polynomial expression.

C) Generation of error evaluation polynomial First, as an initial setting, syndromes 81 to S8 are entered into the registers 101 to 108, and the two output selection circuits 13
Let A be the selection from 0 to 138 and 140 to 148. On the other hand, by performing the same operation as when generating the error locator polynomial, the outputs of registers 101 to 108 can be changed to It can also be found by executing.

First, as an initial setting, clear registers 100 to 108, and 2-man power 1 output selection circuits 130 to 138 and 140 to 14.
8 is selected as B, and data D is received from the input terminal. ,D.

-4,...,D2. Input D□ in sequence. Registers 101 to 10 after inputting all received data
The value of 8 becomes the syndrome 87-So, and then the selection of the two-man power 1-output selection circuits 130-138, 140-148 is set to A, and the error position information X is input from the input terminal, x2.
Input x,, ・. Coefficients ω7 to ω whose values in registers 101 to 108 at the time when input of all error position information is completed correspond to each term of the error evaluation polynomial. bawl.

In this way, with the configuration of this embodiment, the number of Galois field multipliers used to generate the polynomial for error correction calculation can be reduced, and the circuit scale can be reduced.

〔Effect of the invention〕

According to the present invention, generation of error correction calculation polynomials (syndrome polynomial/error locator polynomial/error evaluation polynomial) in erasure correction of Reed-Solomon codes can be performed by two people and one person.
By changing the selection of the output selection circuit and executing the process, the number of Galois field multipliers used can be reduced, and the circuit scale can be reduced.

Further, by connecting the calculation means consisting of a register, a Galois field adder, a multiplier, and two two-man power one-output selection circuits in parallel in 2t+1 stages, polynomial generation calculations can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a polynomial generation circuit for error correction calculation as an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional syndrome polynomial generation circuit, and FIG. 3 is a conventional error locator polynomial generation circuit. FIG. 4 is a block diagram showing a conventional error evaluation polynomial generation circuit. 1oO~108,200~207,300~308.3
10-317...Register, 110-118,
210~217, 320~327.421~427...
... Galois field adder, 120~128,220~
227,330~337.430~437...
Galois field multiplier, 130-138, 140-148・
...2-person power 1-output selection circuit. Atsushi 1 figure

Claims (1)

[Scope of Claims] 1. A Reed-Solomon code for t-fold error correction whose code word is composed of elements of a Galois field GF (2^m) that satisfies a modulus polynomial of m (m = 1, 2, ...) error correction method that generates coefficients for each polynomial of the syndrome polynomial, error locator polynomial, and error evaluation polynomial when decoding is performed using an erasure correction method that uses a pointer that indicates the position of data that is considered to be an error in advance. In the arithmetic polynomial generation circuit, a first selection circuit inputs input data and a root of an error correction parity generation polynomial or specific data, and selects and outputs either one; A Galois field multiplier that multiplies the output of the register by the output from the register and outputs the multiplication result, and a second multiplier that receives input data or specific data and output data, selects one, and outputs a selection circuit; a Galois field adder that adds the output from the second selection circuit and the output from the multiplier and outputs the addition result; and a Galois field adder that temporarily stores the output from the adder; The arithmetic means consisting of the above-mentioned output register and the like are arranged in 2t+1 stages from upper to lower, and the output of the register of each arithmetic means is sent to the second selection circuit of the arithmetic means one stage lower. In addition to inputting the output data, common data is input to the first output data of each calculation means.
and a second selection circuit as the input data, and obtain coefficients of each polynomial of the syndrome polynomial, error locator polynomial, and error evaluation polynomial from the output of the register of each calculation means, respectively. Arithmetic polynomial generation circuit.