JPH03190327A - Error correction circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a division circuit and to reduce the circuit scale by using a hardware for coding in common with the hardware used for decoding. CONSTITUTION:In the case of decoding, a syndrome generating circuit is used to obtain a syndrome series from a reception code series. Then an error is judged from the syndrome series and when any error exists, a ROM 3 is used to obtain an error number, an error location and an error pattern is obtained to correct the error. In the case of coding, the hardware used for decoding is used. Then a syndrome generating circuit 1 generates a syndrome with a redundant series set to 0 is generated and an inverse matrix H<-1> stored in the ROM 3 is used and a definite field arithmetic circuit 2 obtains a redundancy series to execute the coding. Thus, an exclusive circuit for coding is not required and the circuit scale is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to an apparatus for transmitting and recording information, and particularly to a circuit for correcting errors.

[Prior Art] In conventional error correction circuits, when obtaining a redundant code sequence, a method has been adopted in which an information polynomial is divided by a generator polynomial. For example, the generator polynomial...+β1x+β. In this case, it can be realized by a circuit as shown in FIG. The circuit shown in FIG. 2 is a generator polynomial division circuit, in which each register 5 is set to O and each coefficient of the information polynomial, that is, the information code sequence is input to the information code sequence 6 manually.
Finally, a redundant code sequence can be obtained in each register 5 by inputting the code into each register 5 through the modulo 2 adder 8 and setting it in the register 5.

[Problem to be Solved by the Invention J] The conventional error correction circuit described above requires a dedicated circuit as shown in FIG. 2 for encoding, which has the disadvantage of increasing the circuit scale.

The purpose of the present invention is to eliminate the need for a dedicated circuit for encoding;
Therefore, it is an object of the present invention to provide an error correction circuit with a small circuit scale.

[Means for Solving the Problems] The error correction circuit of the present invention includes a syndrome generation circuit that generates a syndrome of a received code sequence, and, in the case of decoding, an error correction circuit that generates a syndrome from the received code sequence by the syndrome generation circuit. If there is an error, the number of errors, error position, and error pattern are determined and error correction is performed. In the case of encoding, an encoded sequence is determined from the syndrome determined by the syndrome generation circuit. Calculation on a finite field. The finite field arithmetic circuit has a finite field arithmetic circuit that can perform the following, and a ROM that stores information for the finite field arithmetic circuit to determine the number of errors, error positions, error patterns, and various tables for determining the encoding sequence.

[Function] The present invention shares the circuit necessary for decoding with the circuit necessary for encoding.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an error correction circuit according to the present invention.

A syndrome generation circuit 1 generates a syndrome of a received code sequence. The finite field arithmetic circuit 2 is a circuit that performs finite field arithmetic, and performs error correction by determining the error state, determining the number of errors, error positions, and error patterns based on the syndrome obtained from the syndrome generation circuit 1. A ROM (read-only memory) 3 stores various tables necessary for the finite field arithmetic circuit 2, such as backlighting in multiplication and exponent expression values for vector expression values.

In the case of decoding, the syndrome generation circuit 3 calculates a syndrome sequence from the received code sequence.

Then, judge the error based on this syndrome series,
If there is an error, the number of errors, error position, and error pattern are determined using the ROM 3, and error correction is performed. In the case of encoding, conventionally a method using a division circuit as shown in FIG. 2 has been used, but the present invention uses hardware used in decoding.

The currently input information sequence U n-,, U n-, .-
,U.

For, the redundant sequence U, , U, ,..., U o
satisfies the following formula (where n>m).

U(α')=O, U(α1)=o,..., U(α1-
1)=O However, U(X) =4Jn-,x"-' +Un-z X'"
-2+-・+Usa-+ xs-t +・・-+U+
X+U.

Here, all the redundant sequences are Ol, that is, U o =U
1 = "" = U-r = O, and the corresponding equation is V (X).

VEX) = [J, -, x'-+ +un-z xn-2
+-・+U,

S ea-2=V (a ”-2), ..., S+
=V (al.

S O” V (α0).

Then, U” [U-t, U-z, “・, Uol” S
= [Slm-1,511m-1""+SO]",
Since HU=S is satisfied, the inverse matrix of H)(-1
Find the redundant sequence U1-1...U by U=H-'S
o can be calculated. Syndrome generation circuit 1 generates a syndrome when O is a redundant series, and RO
Using the inverse matrix H-1 stored in M3, the finite field arithmetic circuit 2 obtains a redundant sequence, thereby performing encoding.

[Effects of the Invention] As described above, the present invention has the effect of making the division circuit unnecessary and reducing the circuit scale by sharing the hardware used for encoding with the hardware used for decoding.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the error correction circuit of the present invention, and FIG. 2 is a block diagram of a conventional encoding circuit. 1... Syndrome generation circuit, 2... Finite field calculation circuit, 3... ROM, 4...
- Information code series input, 5... Register, 6... Information code series input, 7... Coefficient multiplier, 8... Modulo 2 adder.

Claims (1)

[Scope of Claims] 1. A syndrome generation circuit that generates a syndrome of a received code sequence; and in the case of decoding, an error is determined from the syndrome sequence obtained from the received code sequence by the syndrome generation circuit, and if there is an error, , a finite field calculation circuit capable of performing calculations on a finite field, which calculates the number of errors, error positions, and error patterns and performs error correction, and in the case of encoding, calculates a coded sequence from the syndrome determined by the syndrome generation circuit; An error correction circuit comprising a ROM in which a finite field arithmetic circuit stores information for determining the number of errors, error positions, error patterns, and various tables for determining a coding sequence.