JPS6345923A - Syndrome calculation circuit - Google Patents

Abstract

PURPOSE:To calculate plural different syndromes by multiplying an output of a 2nd register and a constant in a Galois field GF(2<m>) in a multiplier circuit selectively in response to a syndrome and giving its output to other input terminal of an exclusive OR circuit. CONSTITUTION:In calculating a syndrome S0, an output of a register 43 is made zero forcibly by a reset signal 48. Then the data symbol dn-1 inputted at first and an output of the register 43 are exclusively ORed by an exclusive OR circuit 41 and its output is inputted to a register 42. The register 42 uses a clock signal 46 to hold the data dn-1, which is outputted to a data selector 44. In the calculation of a syndrome S1, a value dn-1.alpha is calculated by an alpha multiple circuit 45 by using the value dn-1 outputted from the register 43 and the result is outputted to the data selector 44. Similarly, in multiplying the output of the register 43 thrice by the circuit 45, the syndrome S3 is obtained. That is, the syndrome Si is obtained by the i-time of multiplication.

Description

[Detailed description of the invention] [Industrial field] The present invention relates to a syndrome calculation circuit.

[Conventional technology]

In digital data storage devices using magnetic disks, optical disks, etc., error correction codes such as Rito-Solomon or BC11 codes are used to improve data reliability.

When decoding data having such an error correction code, syndromes are first calculated.

A conventional syndrome calculation circuit for calculating this syndrome will be explained with reference to FIG.

FIG. 4 is a block diagram of a syndrome calculation circuit for a triple-error Reed-Solomon code encoded according to the parity check matrix H. In this syndrome calculation circuit, syndromes SO+Sl+S2 . S3. S4
．． Calculate S5 using the following formula.

Here, do, d+, dz, ”−, d,, −+ is one code word (symbol d1
is m bits). It is assumed that equation (2) and subsequent operations between symbols are performed on the Galois field CF(2w').

When actually performing syndrome calculations, for example, when determining Sl, it is calculated sequentially as shown in the following equation.

s, = (-(d, I ・α→-d,,-2)・α
+dn-3)・α+-+d0) In Figure 4, 10 to 15 are m-bit exclusive OR circuits, 20 to 25 are m-bit registers, and 31 to 35 are elements on GF(2'''), respectively. α, α2.α3.α4.α
A circuit for multiplying by 5 is shown. Here, exclusive OR circuit 10
The exclusive OR circuit 11, the register 21, and the α multiplication circuit 31 are the calculation circuits for the syndrome S0, the exclusive OR circuit 12, and the register 22.
and α2 multiplication circuit 32 converts the calculation circuit of S2 into exclusive OR
The circuit 13, register 23 and α3 multiplication circuit 33 convert the calculation circuit of S3 into the exclusive OR circuit 14, register 24 and α3
4 multiplier circuit 34 converts the calculation circuit of S4 into exclusive OR circuit 1
5, the register 25 and the α5 multiplication circuit 35 constitute the calculation circuit of S5.

The calculations of syndromes 50 to S5 are performed by inputting one data symbol via the data symbol input signal line d, and
It is executed by applying a clock to registers 20 to 25, and when all data input is completed, registers 20 to 25 are
The contents of are (direct) for syndromes 30 to S, respectively.

[Problem that the invention seeks to solve]

However, the conventional syndrome calculation circuit described above requires an m x 6 bit exclusive OR circuit and an m x 6 bit register, and also requires α.

α2. α3. α4. If a ROM is used for the α5 multiplier circuit, five 21×m-bit ROMs are required.

That is, if the number of error correction symbols is t, then in the heavy error correction Reed-Solomon code, an m x 2t bit exclusive OR circuit, an m x 2t bit register, 2 II x
(2t-1) m-bit RORs are required. Therefore, in a triple-corrected Reed-Solomon code of 1 symbol - 1 byte (m-8), 48-bit exclusion (lh OR
Circuit, 48-bit register, 256 x 8-bit RO
Five M will be required.

In this way, in the conventional syndrome calculation circuit, two separate syndrome calculation circuits are required depending on t for Reed-Solomon or BCH codes with large t.
There is a problem that the circuit scale increases.

The present invention was made in view of these conventional problems, and an object of the present invention is to provide a syndrome calculation circuit appropriately configured so that the circuit scale can be reduced even when the number t of error correction symbols becomes large. do.

[Means and effects for solving the problem] In order to achieve the above object, the present invention uses a Galois field GF (2″)
(m is any integer) above Reed Solomon or BC)
In a syndrome calculation circuit that calculates a plurality of syndromes from an I-encoded codeword, an exclusive OR circuit that inputs a codeword symbol to one input terminal, and an exclusive OR circuit that inputs a codeword symbol to one input terminal;
a first register that holds the output of the R circuit; a data selector that inputs the output of the first register to one input terminal; and a data selector that holds the output of the data selector and inputs the output of the first register to the other input of the exclusive OR circuit. a second register feeding the end;
The Galois field GF (
a multiplier circuit that multiplies the output of the second register and the Galois field GF( A plurality of different syndromes can be calculated by multiplying by a constant of Configure it like this.

〔Example〕

FIG. 1 is a schematic diagram showing an embodiment of the present invention.

In FIG. 1, 41 is an m-bit exclusive OR circuit;
2.43 is an m-bit register, 44 is a data selector with 2m-bit input and m-bit output, and 45 is GF (2m''
) shows a multiplication circuit that multiplies the element α above. The register 42 holds and outputs the input data at the rising edge of the clock signal 46, and the register 43 holds and outputs the input data at the rising edge of the clock signal 47, and at the same time sets the output to zero with the reset signal 48. Further, the data selector 44 outputs either one of the two input systems according to the select signal 49. In this example, when the select signal 49 is at a low level "F", the output of the register 42 is output at a high level rH.
When J, the output of the α multiplication circuit 45 is supplied to the register 43.

The operation of the syndrome calculation circuit shown in FIG. 1 will be described below with reference to the timing charts shown in FIG. 2 (al to (C1).

FIG. 2 fal shows a timing chart for calculating the syndrome S0. First, the output of the register 43 is forced to zero by the reset signal 48.

Next, the exclusive OR circuit 41 performs an exclusive OR operation on the first input data symbol dn-1 and the output of the register 43 via the data symbol input signal line d, and inputs the output to the register 42. . In this case, d7-3 is input to the register 42. The register 42 holds d, , -1 in response to the clock signal 46 and outputs this to the data selector 44. Since the select signal 49 is "L", the data selector 44 selects the output dn-1 of the register 42 and inputs it to the register 43.

The register 43 holds d7-1 in response to the clock signal 47 and outputs it to the exclusive OR circuit 41 and the α multiplier circuit 45. Here, the operation of the α multiplication circuit 45 is not a problem. Next, the second data symbol d, -2 inputted via the data symbol input signal line d and the register 43
The exclusive OR circuit 41 performs exclusive OR with the outputs d, , -1 of
The output d7-1dn-2 is input to the register 42. Similarly, d. When all the data up to this point have been input and the clock signal 46 is applied to the register 42, the contents of the register 42 at that time become (direct) of the syndrome S0.

FIG. 2 (bl shows a timing chart for calculating the syndrome S1. First, the output of the register 43 is forced to zero by the reset signal 48.

Next, the exclusive OR circuit 41 performs an exclusive OR operation on the data symbol dn-1 input first through the data symbol input signal line d and the output of the register 43, and the output d
+i-1 is input to register 42. The register 42 is
d due to clock signal +346. -1 is held and the error is output to the data selector 44. The data selector 44 is
Since the select signal 49 is [LJ, the output d of the register 42
. -1 is selected and output to the register 43. The register 43 holds dn-1 by the clock Shingetsu 47,
This is output to exclusive OR circuit 41 and α multiplication circuit 45. The actions up to this point are S. This is exactly the same as in the case of . However, in calculating this Sl, dl-1 output from the register 43 causes the α multiplication circuit 45 to
- Calculate α and output the result to the data selector 44. Since the select signal 49 is rHJ, the data selector 44 selects the output dn-1·α of the α multiplication circuit 45 and outputs it to the register 43. The register 43 holds dn-1・α by the clock signal 47 and outputs it exclusively to O.
The signal is output to the R circuit 41 and the α multiplication circuit 45, but the operation of the α multiplication circuit 45 is not considered here. Next, the exclusive OR circuit 41 performs an exclusive OR operation on the second data symbol dn-2 input via the data symbol input signal line d and the output dn-1.α of the register 43, and the output d
Input n-1·α@dn-2 to the register 42. In the same manner, when all the data up to do is inputted and the clock signal 46 is applied to the register 42, the contents of the register 42 at that time become the value of the syndrome S1.

FIG. 2 (C1 shows a timing chart for calculating syndrome S2. The difference from the calculation of syndrome S1 is: The only difference is that the output of is multiplied by α by the α multiplication circuit 45 once in the case of syndrome S1 and twice in the case of syndrome S2. Obtained.

Similarly, the output of the register 43 is multiplied by the α multiplication circuit 45.
Multiplying by α times yields S3. That is, by performing one multiplication, S can be calculated in the same circuit.

The syndrome calculation circuit shown in FIG.
If it is a bit, one m-bit exclusive OR circuit 41
, two m-bit registers 42 and 43, and one 2
a data selector 44 with m-bit input and m-bit output;
If RO)'I is used in the multiplier circuit 45, 2'''×m
Since it can be configured with a bit ROM, the circuit scale can be made very small.

In this way, according to this embodiment, no matter what value t is, the same circuit can perform the syndrome 0-m So+S
Since all of ++ −'5zt−+ can be calculated, the circuit scale can be configured to be small.

Note that the α multiplication circuit 45 can perform exclusive OR operation without using ROM.
It can also be realized by configuring Figure 3 shows α as Galois field GF
(2B) As the element above, the primitive polynomial XB+X'+X34X
This shows the configuration of the α multiplier circuit when +1 = root of O, where 51 is an input terminal, 52 is an output terminal, and 53 is an exclusive OR circuit.
If M is not used, the circuit scale can be made even smaller.

〔Effect of the invention〕

As described above, according to the present invention, different syndromes can be calculated using the same circuit, so that the scale of the syndrome calculation circuit can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the α multiplication circuit shown in FIG. A diagram showing the configuration of another example, and FIG. 4 is a diagram for explaining the conventional technology. 41-Exclusive OR circuit 42.43-Register 4
4 Data selector 45-α multiplication circuit 51-input terminal 52-output terminal 53-exclusive OR circuit Patent Applicant Olympus Optical Industry Co., Ltd. Figure 2 (a)

Claims (1)

[Claims] 1. In a syndrome calculation circuit that calculates multiple syndromes from Reed-Solomon or BCH encoded codewords on the Galois field GF(2^m) (m is any integer), the codeword symbol is input to one input terminal. an exclusive OR circuit input to the
a data selector that inputs the output of the first register to one input terminal, and a second register that holds the output of the data selector and supplies it to the other input terminal of the exclusive OR circuit. , a multiplication circuit that multiplies the output of the second register by a constant on the Galois field GF(2^m) and supplies the result to the other input terminal of the data selector, In the multiplication circuit, the output of the second register and the Galois field GF
A plurality of different syndromes can be calculated by multiplying by a constant above (2^m) and supplying the output to the other input terminal of the exclusive OR circuit via the data selector and the second register. A syndrome calculation circuit characterized by being configured as follows.