JPS63236364A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to reduce the resistance of a resistance layer by limiting a region to ion-implant in a channel. CONSTITUTION:A P-type well is formed in the surface of a P-type (can be an N-type) 10OMEGA.cm substrate and thereafter, an SiO2 layer 2 is formed and a negative resist 4 is applied to the surface. Then, a photo etching is performed using a gate as a mask to remove the resist on a place where the gate is formed in the future and an ion-implantation for controlling a threshold value is performed to make high locally the concentration of acceptors in a channel part. After that, the resist and the SiO2 layer are removed from the entire surface and a gate insulating layer is formed on the surface. Moreover, poly silicon is applied to the whole surface and a gate electrode 5, N<-> impurity diffused layers 8, a side spacer 9, N<+> diffused layers 7 and contact electrodes 6 and 10 are formed by a conventional process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor device particularly suitable for lowering the diffusion layer resistance by limiting the area where ion implantation for threshold control is effectively performed, and its manufacture. Regarding the method.

[Conventional technology]

Conventionally, the problem of diffused layer resistance has been discussed in the V.L.N.I. Symposium (1986), pages 27 to 2.
8 pages (VLSI Sy+++posium 19
86°pp, 27-28).

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration the point of eliminating the highly concentrated boron implanted into the source/drain diffusion layer region of the n-channel MOS transistor, which poses a problem in realizing low resistance of surface channel type devices. was there.

An object of the present invention is to attempt to reduce the resistance of the diffusion layer by limiting the region of channel ion implantation.

[Means for solving problems]

The above object is achieved in a conventional process by performing a photolithography step before forming the gate electrode to separate the regions where the threshold control ion implantation is performed and the regions where the threshold control ion implantation is not performed or removed.

[Effect]

When forming an n-channel transistor, not implanting boron for threshold control into the source/drain region or removing implanted boron by etching has the effect of lowering the resistance of the diffusion layer.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. For example, a P well is formed on the surface of a p-type (or n-type) 10Ω substrate using a conventional process, and then 5iOz, 2
A negative resist 4 is applied to the surface. This gate insulating film may be made of a high dielectric material such as T a 20a, N, or z○8 in addition to SiO2.

Next, photolithography is performed using a gate mask to remove the resist where the gate will be formed in the future.

Perform ion implantation for threshold control.

Through the above process, the acceptor concentration in the channel portion is locally increased. After that, resist and SiO2
is completely removed and a gate insulating layer is formed on the surface. Furthermore,
Polysilicon is applied to the entire surface and the gate electrode 5. is formed using a conventional process. n- impurity diffusion layer 8. Side spacer9.
An n+ diffusion layer 7 and contact electrodes 6 and 10 are formed.

FIG. 2 shows a cross-sectional view of an n-channel LDDMOS transistor formed by this process. FIG. 3 shows a cross-sectional view when the present invention is applied to an n-channel p-pocket LDD transistor. According to the present invention, there is an effect of reducing the resistance of the n-diffusion layer.

An embodiment will be described with reference to FIG. 4 in which the invention set forth in claim 3 is applied as the structure set forth in claim 1. As in Example 1, after Si○2 is formed on the surface of the substrate, ion implantation for threshold control is performed on the entire surface. Next, a positive resist is applied to the surface, photolithography is performed using the gate as a mask, and the resist is removed leaving only the resist in the area that will become the gate in the future. Etching is then performed using this resist as a mask to remove the Si substrate including SiO2 and the high concentration acceptor region on the surface implanted by ion implantation for threshold control. New Si is formed so that it becomes flat. (Area numbered 12) This S
i may be p-type or n-type, but if it is p-type, it must be lower than the peak concentration of the p-well. Then, the resist is removed, a gate insulating film 2 is formed on the entire surface, polysilicon is deposited, and a gate electrode 5. Side spacer, n-diffusion layer.

n1 diffusion layers and contact electrodes are formed. Here, the diffusion layer is formed by ion implantation.

The present invention can be applied to an n-channel LDD transistor and an n-channel p-pocket LDD transistor as in the first embodiment, and the cross-sectional view is as shown in FIG. 2.3. According to the present invention, in fact, the same effects as in Example 1 can be obtained.

FIG. 5 shows a second embodiment of the invention as set forth in claim 3. Similarly to the first embodiment, Sj, O
z is formed, a negative resist is applied to the entire surface, and photolithography is performed using the gate as a mask. Then, the resist and 5iOz in the area where the gate will be formed in the future are removed, and the Si substrate is etched by 0.05 μm using the resist as a mask. Next, a p-type Si substrate is formed on the removed portion by epitaxial growth so that the surface of the Si substrate is flat. The concentration of this Si substrate is assumed to be higher than the peak concentration of the p-well. (Region numbered 13) Next, the resist and 5iOz are all removed, a gate insulating film 2 is formed on the entire surface, polysilicon is deposited, and the gate electrode 5. Form side spacers, an n-diffusion layer, an n-diffusion layer, and a contact electrode. However, here, the diffusion layer is formed by ion implantation.

The present invention can be applied to an n-channel LDD)-transistor and an n-channel P pocket DD transistor similar to the first embodiment, and the cross-sectional views are as shown in FIGS. 2 and 3. Furthermore, the present invention provides the same effects as in Example 1.

FIG. 6 shows a third embodiment of the invention set forth in claim 3. As in the first embodiment, Si□t is applied to the substrate surface.
After forming, ion implantation for threshold voltage control is performed on the entire surface. Next, a positive resist is applied to the surface, photolithography is performed using the gate as a mask, and the resist is removed, leaving only the resist in the area where the gate will be formed in the future. and,
Using this remaining resist as a mask, etching is performed to remove SiO2 and Si containing the high concentration acceptor region on the surface implanted by ion implantation for threshold voltage control.
Remove the board. After that, partial epitaxial growth is performed, and n-type S is grown so that the surface of the Si substrate is flat.
form i. (Figure 14) The impurity concentration of this n-type Si substrate must be at least one order of magnitude lower than the peak concentration of the n10 diffusion layer that will be formed later by ion implantation. Next, remove all resist and SiO2,
A gate insulating film 2 is formed on the entire surface, polysilicon 5 is deposited, and a gate f1! is formed by a normal process. Ti
5. Side spacers, n+ diffusion layers and contact electrodes are formed.

7 and 8 show examples in which the present invention is applied to an n-channel LDD)-transistor and an n-channel p pocket transistor.
Shown below. Further, the present invention provides the same effects as in Example 1.

FIG. 9 shows a second embodiment of the invention set forth in claim 2. As in the first embodiment, a gate insulating film is formed on the surface of the Si substrate on which a p-well is formed. Next, a focused ion beam is used to locally implant ions into the region that will become the gate in the future for threshold control purposes. Thereafter, a gate electrode, an n-diffusion layer, side spacers, an n-diffusion layer, and a contact electrode are formed by a normal process.

FIG. 9 shows a cross-sectional view when the present invention is applied to an n-channel LDD transistor. The present invention has the same effect as Example 1. The present invention is also applicable to an n-channel p-pocket transistor, a cross-sectional view of which is shown in FIG. In this case as well, the same effects as in the first embodiment can be obtained.

〔Effect of the invention〕

According to the invention, especially high? Since the resistance of the n-diffusion layer of the LDD structure which requires a degree E implantation can be lowered, there is an effect of increasing the current value in the saturated operation region.

[Brief explanation of drawings]

1, 2, and 3 are sectional views of a first embodiment of the present invention, FIG. 4 is a sectional view of a second embodiment, and FIG. 5 is a sectional view of a third embodiment, Figures 6 and 7. FIG. 8 is a sectional view of the fourth embodiment, and FIG. 9 is a sectional view of the fifth embodiment. 1... Semiconductor substrate, 2... Gate insulating film, 3...
Channel region, 4... Resist, 5... Gate electrode, 6... Gate electrode contact, 7... N- impurity diffusion layer, 8... N- impurity diffusion layer, 9... insulating film,
10... Source/drain contact electrode, 1...
p-type head region, 12... semiconductor substrate (formed by epitaxial growth), 13... p-type semiconductor substrate (formed by epitaxial growth), 14... n-type semiconductor substrate (formed by epitaxial growth). Agent: Patent Attorney Katsuo Ogawa

Claims (1)

[Claims] 1. At least a gate electrode, a gate insulating film, a semiconductor layer,
1. A semiconductor device comprising source/drain regions, wherein an impurity region for threshold control is provided in a semiconductor layer other than the source/drain regions. 2. In the method of manufacturing a semiconductor device including a gate electrode, a gate insulating film, a semiconductor layer, and a source/drain region, the ion implantation for threshold control is performed under the gate electrode or outside the gate electrode. 1. A method of manufacturing a semiconductor device, characterized in that: 3. In the method for manufacturing a semiconductor device according to claim 2, epitaxial layer formation is performed in the regions where the threshold control ion implantation is performed and the regions where the threshold control ion implantation is not performed. A method for manufacturing a semiconductor device, characterized in that it is realized by performing the steps separately.