JPS63228254A - Dma controller - Google Patents

Abstract

PURPOSE:To easily transfer data from a two-dimensionally arranged memory only by one setting by calculating the sum (or difference) between the value of an address register and that of an address operation register and storing the calculated result in the address register. CONSTITUTION:The DMA controller 12 is provided with an auto-initializing register 13 for setting up the frequency of auto-initializing in each channel, an address operation register 16 to be used for resetting an address at the time of generating auto-initializing and a means for storing the sum or difference between the contents of the registers 14, 16. In case of transferring data from the I/O to the two-dimensionally arranged memory, the transfer of all the data can be attained by setting up the registers 14 and a count register 15 in the DMA controller 12 only once.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to a DM used with a microprocessor.
Regarding the A controller.

(Prior Art and its Problems) Conventionally, in this type of DMA controller, the method of accessing the memory has been one-dimensional. That is, a single setting from the microprocessor can only transfer data from consecutive memory addresses. Now, consider memory addresses arranged horizontally by X words horizontally and by Z words vertically. If the first memory address is O, then the memory address of the first line is 0, 1, . ..., x-1,2
Lines are X, X + 1, -, 2 X -
1. A line port is Ca-1)X, (CE-1)X+1
．． -, aX I. When arranged in this way, if the DMA controller is used to move the square area (one line is smaller than X words) in the shaded area in FIG. 3 to the area in the shaded area in FIG. Address registers and count registers had to be set for each line in the controller, which placed a huge burden on the microprocessor, and the proportion of this processing in the software increased, making the software even more complex. .

(Objective of the Invention and Means for Solving Problems) The present invention solves these conventional problems, and includes an auto-initialization register, an address operation register, an address register, and an address operation register for each channel of a DMA controller. The purpose of this invention is to provide an excellent DMA controller that can perform two-dimensional memory access by providing means for calculating the sum (or difference) of and storing it in an address register. be.

(Function) Therefore, according to the present invention, by one setting from the microprocessor, (
This has the advantage that data transfer (or to memory) can be easily performed.

(Example) FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 11 is a microprocessor that sets addresses, count information, etc. in the DMA controller 12;
13 to 22 classify the DMA controller 12 by function and register type, 13 is a register for setting the number of auto-initializations (herein referred to as an auto-initialization register), and 14 is a DMA controller 12
address register used when generating an address,
15 is a count register in which the number of data transfers is set by the DMA controller 12, and 16 is an address register 14 that is set when auto-initialization occurs.
17 is a control register for setting the DMA controller 12 with control information such as data bus width, bus mode, DMA request level, DMA ACK level, mode, etc., and 18 is a series of registers for performing numerical operations. 19 is an address generator that generates an address for the memory; 20 is a register that indicates which memory address the DMA transfer is currently being performed to; 21 is a timing generation unit that controls the timing of control signals, addresses, etc. for memory or Ilo; 22 is a control unit that controls the registers and functional parts from 13 to 21; be. In FIG. 1, arrows (arrows) mean that the microprocessor 11 sets commands, control information, etc. to the DMA controller 12. Also, the arrow (←.

→) is an external DMA request and DMAACK control signal.

Next, the operation of the above embodiment will be explained using the flowchart shown in FIG. Now, consider that the DMA controller 12 with a 16-bit data bus width transfers data from Ilo, which has a data bus width of 16 bits (one word), to a memory with a data bus width of 16 bits. Here, it is assumed that channel O of the DMA controller 12 is used, and control register 1 of the DMA controller 12 is used.
7 has already been set by the microprocessor 11. First, in step 31, the microprocessor 11 sets the number of times auto-initialization is to be performed in the auto-initialization register 13 of the DMA controller 12. In the process of step 32, the microprocessor 11 sets the beginning of the data transfer destination address in the address register 14 of the DMA controller 12.

In the process of step 33, the microprocessor 11
Address information to be added to (or subtracted from) the address register 14 when auto-initialization occurs in the address operation register 16 of the A controller 12 is set. During step 34, the microprocessor 11 registers the count register 15 of the DMA controller 12.
The number of times a series of DMA operations will be performed is set in . In the course of step 35, the contents of the count register 15 are transferred to the temporary count register 18. During step 36, the contents of address register 14 are transferred to temporary address register 20. In the process of step 37, it is determined whether there is an external DMA request.

If there is no DMA request, the process returns to step 37. If there is a DMA request, a DMA operation is performed in step 38. In the process of step 39, the contents of the temporary count register 18 are decremented by one. In the process of step 40, it is determined whether the content of the temporary count register 18 is O. If the content is 0, the content of the auto-initialize register 13 is decremented by 1 in the process of step 41. In the process of step 42, if the content of the auto-initialize register 13 is 0, the DMA operation is terminated. If the content of the temporary count register 18 is not O in the process of step 40, then 2 is added to the content of the temporary address register 20 in the process of step 43, and the process returns to step 37. In the process of step 42, if the content of the auto-initialize register 13 is not O, in the process of step 44, the address register 14
and the contents of the address operation register 16 are transferred to the address register 14, and step 35
Return to the process.

As described above, according to the above embodiment, when data is transferred from Ilo to two-dimensionally arranged memory, the settings from the microprocessor 11 to the address register 14 and count register 15 of the DMA controller 12 are , all transfers can be performed only once.

Furthermore, by using two channels of the DMA controller 12, all data transfer between memories can be performed by one setting for memory addresses arranged two-dimensionally.

(Effects of the Invention) As is clear from the embodiments described above, the present invention is applicable when data is transferred from a two-dimensionally arranged memory to Ilo, and when data is transferred from Ilo to a two-dimensionally arranged memory. When transferring data from two-dimensionally arranged memory to two-dimensionally arranged memory, the effect is that all data transfer can be completed with one setting to the DMA controller 1-roller. It has the following.

[Brief explanation of drawings]

FIG. 1 is an internal block diagram of a DMA controller in an embodiment of the present invention, FIG. 2 is a flowchart for explaining an example of a program for controlling the DMA controller and an example of the operation of the DMA controller, 3
4 and 4 are explanatory diagrams when data is transferred from two-dimensionally arranged memory to memory. DESCRIPTION OF SYMBOLS 11... Microprocessor, 12... DMA controller, 13... Auto initialize register, 14... Address register, 15... Count register, 16... Address operation register, 17... Control register , 18...
・Temporary callan l register, 19...Address generation section, 20...Temporary address register,
21... Timing generation section, 22... Control section. Patent Applicant: Matsushita Electric Industrial Co., Ltd. 1st Cause D M A So C Rini Est Figure 3 Figure 4

Claims (1)

[Claims] Has data transfer function between memory and memory, data transfer function between memory and I/O, auto-initialization function, DMA request for multiple channels, address register, count register, temporary address register, and temporary count register that can be set for each channel. In a DMA (direct memory access) controller, there is an auto-initialize register that can set the number of auto-initializations for each channel, an address operation register that is used to reset the address when auto-initialization occurs, and an address register and address operation. A DMA controller comprising means for storing the sum or difference of register contents in an address register.