JPH01181142A - Parity control system for dual port memory - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of parity errors in a read state by writing the dummy data into a sub-memory SAM forming a dual port memory and then transferring the data to a RAM from the SAM even in case the number of data transferred and written into the SAM is smaller than the capacity of the SAM. CONSTITUTION:A DMA control circuit 4 counts the data which are transferred and written into a SAM1-1 forming a dual port memory 1. If the count value of the data is smaller than the capacity of the SAM1-1, the remaining dummy data (with parity) are transferred and written to the SAM1-1. Then data are transferred to a RAM1-2 from the SAM1-1. In such a constitution where the dummy data written even in case the number of data transferred to the SAM1-1 is smaller than the capacity of the SAM1-1, no parity error occurs when data are read out.

Description

[Detailed Description of the Invention] [Summary] Regarding a parity control method that adds a parity bit to data written to a dual-port memory, when residual data is generated in the SAM of the dual-port memory, dummy data with a parity bit added is generated. write,
For the purpose of improving reliability, a parity bit is added to the data and written to the SAM that constitutes the dual port memory, and the number of writes is counted and if the capacity of the SAM is not reached, the data is It is configured to write dummy data with parity bits added for the capacity.

[Industrial application field]

The present invention relates to a parity control method that adds a parity bit to data written to a dual port memory.

[Problems to be solved by conventional technology and invention] Dual port memory has only one input/output port like DRAM.
This solves the problem of reduced processing speed due to bus contention, which occurs due to the fact that the controller has multiple input/output ports, and allows effective data transfer with a small amount of memory. When performing data transfer using this dual port memory, it is essential to add a parity bit to the data in order to improve the authenticity of the data. However, as shown in Figure 3, dual port memory has an internal D
There is a problem in that parity is destroyed because block transfer is performed between the RAM 21-2, which is a RAM, and the SAM 21-1, which is a sub-memory. A brief explanation will be given below using FIGS. 3 and 4.

As shown in FIG. 3, a parity generator/chiever 22 adds a parity bit to the data received by the communication control LSI 23, and sends both of them to the SAM that constitutes the dual port memory 21 via a data bus.
DMA transfer and write to 21-1. At this time, as shown in Figure 4 (
b) DMA transfer was performed and written to SAM21-1 as shown by the diagonal line downward to the left, but as shown by the vertical line in the figure, an area where parity bits are not written occurs in SAM21-1. . When the contents of the SAM 21-1 are block transferred and written to the RAM 21-2 in the state shown in FIG. 4 (a), a parity bit is added to the area A D + in FIG. Sometimes parity errors do not occur. However, area A D
As for z, no parity bit is added and there is a problem in that a parity error occurs during reading.

An object of the present invention is to improve reliability by writing dummy data with a parity bit added when residual data is generated in the SAM of a dual port memory.

[Means for solving problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, dual port memory 1 is SAMI
-1 and RAM1-2, etc., and has multiple input/output ports.

Parity error 2-L 2-2 is for adding a parity bit to data.

The DMA control circuit 4 includes the SAMI-1 and the communication control LSI 7.
It controls data transfer between.

[Effect]

In the present invention, as shown in FIG. 1, the DMA control circuit 4
Count the number of data transferred and written to SAM1-1 that constitutes dual port memory 1, and
When the capacity of A M 1 1 is not reached, the remaining dummy data (with parity) is further stored in SAMI.
After data is transferred and written to RAM 1-1, the data is transferred from SAM 4-1 to RAM 1-2.

Therefore, SAM 1 constituting dual port memory 1
-1, the number of data transferred to the corresponding sAM1
Since dummy data (with parity bits) is written even when the capacity is less than -L, parity errors do not occur during reading (and data accuracy can be improved).

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 and 2.

In FIG. 1, the parity checker 3 is SAM1-1
, performs a parity check on data read from RAM1-2.

The DMA control circuit 4 has a timer 5, a register 6, etc., and controls the data transfer between the SAMI-1 and the communication control LSI 7. When this is not achieved, dummy data (with a parity bit) corresponding to the unsatisfied remainder is transferred to SAMI-1.

The memory arbitration circuit 8 transfers data from the SAMI-1 to the RAM l-2 based on instructions from the DMA control circuit 4.

The communication system 41LSI 7 controls data exchange (communication) via a coaxial cable.

Next, the operation of the configuration shown in FIG. 1 will be explained in detail using the flowchart shown in FIG.

In FIG. 2, the symbol (■) in the figure indicates that the communication control LSI 7 notifies the DMA control circuit 4 by an interrupt that data has been received.

■ in the figure indicates that initial settings are to be made. This is shown in the figure.
The DMA control circuit 4, which received the reception notification by an interrupt, sets the start bit 5 of the timer 5 before starting the DMA transfer.
This means that initial settings such as setting -1 and setting the DMA start bit of register 6 are performed.

■ in the figure indicates that the number of data is counted. This is D
The MA control circuit 4 uses the timer 5 to
DM to SAMl-1 via local bus from
This means counting the number of data transferred and written (number of clocks).

■ in the figure indicates that the timer value is K (the capacity value K of SAMI-1,
For example, 256 heights). Y
In the case of ES, data transfer equal to the capacity of SAMI-1 was performed, so the DMA control circuit 4 instructs the memory arbitration circuit 8 to transfer data at ■ in the figure, and transfers data corresponding to the capacity of SAMI-1.
After data is transferred from 1 to RAM 1-2, the timer 5 is cleared at 2 in the figure, and the following steps are executed at 2 in the figure. In the case of NO, and when the completion of reception is notified to the DMA control circuit 4 by an interrupt, the process related to the present invention, that is, the remaining area not written to SAMI-1, After writing dummy data (with parity bit) to the memory, the data is transferred from SAM1-1 to RAM1-2.

■ in the figure indicates that the timer value is read.

This means reading the data transfer number KL stored in the timer 5 provided in the DMA control circuit 4.

■ in the figure indicates that K Ki is calculated, which means
This means calculating the remaining number of data by subtracting the number of transferred data from the capacity of SAMI-1.

■ in the figure indicates that manual transfer bit 6-2 is sent. This is DMA! I] Set the manual transfer bit 6-2 in the register 6 provided in the 13111 circuit 4 and transfer the dummy data to SAMI-1.
It is meant to display what will be written.

In the figure, [phase] represents the remaining (K-Ki) dummy data (
(with parity bit) is written into SAMI-1.

■ in the figure indicates that the DMA control circuit 4 instructs the memory arbitration circuit 8 to transfer data from SAMI-1 to RAM1-1.
2 indicates that data is to be transferred.

As mentioned above, the number of data received by the communication system 411LSI7, DMA transferred to SAMI-1, and written is
When the capacity of the SAMI-1 is not reached, dummy data (with parity bit) corresponding to the remaining capacity
By transferring data and writing, and then transferring data from SAMI-1 to RAM1-2, SAMI
Even if the number of data transferred to -1 is a fraction, no parity error will be detected during reading, making it possible to improve data reliability.

In addition, the SAM is sent from the communication control LSI 7 via the local lotus.
When data is transferred by DMA to I-1, a parity bit is added and written by the parity generator 2-1. In addition, RAM 1-2, SAMI-1
The data (with a parity bit) read out is checked for errors by a parity checker 3 using the parity bit.

〔Effect of the invention〕

As explained above, according to the present invention, even when the number of data transferred and written to SAMI-1 constituting the dual port memory 1 is less than the capacity of SAMI-1, dummy data ( Since it uses a configuration in which data is written (with a parity bit) and then data is transferred from SAMI-1 to RAM1-2, parity errors do not occur during reading, improving data reliability. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the present invention, FIG. 3 is an explanatory diagram of the prior art, and FIG. 4 is an explanatory diagram of the operation of the prior art. In the figure, 1 is a dual port memory, 1-1 is a SAM (sub memory), 1-2 is a RAM, 2-1゜2-2 is a parity generator, 3 is a parity checker, 4 is a DMA control circuit, and 5 is a Timer, 6 is register, 7 is communication control LS
I,8 represents a memory arbitration circuit. , & Light August・Th 6 t B Month Hronayatchi
2 Figure Q7-1

Claims (1)

[Claims] In a parity control method that adds a parity bit to data written to a dual port memory, data is written with a parity bit added to the submemory (hereinafter referred to as SAM) that makes up the dual port memory, and the number of writes is counted. 1. A parity control method in a dual port memory, characterized in that when the capacity of the SAM is not reached, dummy data to which parity bits corresponding to the unsatisfactory capacity are added is written.