JPS60169967A - Information transfer system - Google Patents

Abstract

PURPOSE:To obtain mutual information in two CPUs or more rapidly similarly to the access of internal RAM by a simple constitution consisting of one bit for each I/O port and one bit for a synchronizing port. CONSTITUTION:At first, seven pulses are sent to respective CPUs as reader clocks from a CPUA31. During the period, each CPU sets up the information ''a'' of another RAM information area 47 in an output buffer area. If the number of data bits is eight bits, each data information is serially transffered to other CPUs synchronously with a reference clock. The 8-bit data of a CPUC33 are inputted to an input buffer area in a CPUA31. Then, time corresponding to seven clocks is used for internal processing time. During the period, the data inputted in the input buffer area 42 are transferred in an output buffer area 41 in parallel and also inputted to ''b'' in another RAM information area 47 in accordance with the timing signal of a timing generating circuit 44.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information transfer system for a multi-fCPυ system used in consumer equipment.

[Technical background of the invention and its problems]

Conventionally, when transferring signals between two CPUs, the process shown in Figure 1 (
The structure is as shown in Figure 2. CPU (1) to ci
When transmitting a signal to 'u (21), an interrupt input is normally used. In this case, at the falling edge of the first signal from CPU (1) to CPU 12), CPU (2)
(1) Detects the signal from the general port and enters interrupt operation.
Read the serial signal from PR. Similarly, cp
A signal is also transmitted from ty(2) to CP tJ(11).

If the 140 PUs issue interrupt operations at the same time, there are two processing methods. ■ After both interrupts are released and a certain delay time has elapsed (the delay time is determined by the CPU
and CPU2 are set to different times. ) There is a method of requesting an interrupt again, and a method of setting priorities for CPU1 and CPU2, and the CPU with the lower priority cancels the interrupt operation and starts the read operation of the other CPU. .

The above example is a case of two CPUs, but a similar configuration example can be applied to a multi-system. However, C
As the number of PUs increases, the degree of signal interaction increases, and it is important to consider whether to provide a recognition port as a process for determining which CPU is transmitting, or to provide a determination code as part of the header of the transmitting serial code. Alternatively, it is necessary to determine the code ratio for the data itself, which makes the system complex and increases the amount of time spent on C two-speed reception. FIG. 2 shows a conventional information transfer system in which a common path is provided and transmission and reception are performed in parallel.

The common path does not have to be a tri-state boat; it is also possible to use a general-purpose input/output boat. In this case, it is necessary to insert an interrupt timing control program at the beginning of the interrupt operation program so that, for example, 11...1'' is ignored and one or more output ports are not specified at any time.

It has the advantage of being able to wire or OR the common path, and since it is parallel input/output, the time for transmission and reception can be shortened, but the more multiples are used, the more changes in signal exchange will occur.
This increases the time required for transmission and reception and increases the complexity of the system.

[Purpose of the invention]

In view of the above-mentioned points, the present invention utilizes a simple configuration of two hardware C output ports and one bit of a synchronization boat, so that mutual information of two or more CPUs can be quickly accessed in the same way as accessing internal RAM. The present invention provides an information transfer system that can be used to transfer data to a VTE CPU.

[Summary of the invention]

The present invention provides a mutual transfer RAM area for each of a plurality of CPUs that transfer information, a 1-bit serial input, a 1-bit serial output, and a 1-bit basic clock input/output for synchronization that can be specified by a program. set up a boat,
This allows information on other CPUs to be obtained in the same way as accessing internal RAM.

[Embodiments of the invention]

Hereinafter, the present invention will be described with reference to illustrated embodiments.

FIG. 4 is an external connection diagram of an information transfer system according to an embodiment of the present invention using three CPUs as shown in FIG. 3;

In the same figure, cpUA13D is a (hos) CPU,
CPUB (:Q, CPUC connection corresponds to slave CPU. SAI, 813I, 8CI are serial inputs of each CPU, 8A0.8 Bo, 8 Co are serial outputs. CLK terminal is an input/output port. When the program is initialized, the CPU G31) is set to three CPUBCs as output ports, and the CPUC (three stages are set as input ports).

Needless to say, the same configuration will be used when the number of CPUs increases. Next, the internal configuration of the CPU will be explained with reference to FIG.

In FIG. 5, 41 is an output buffer area, 42 is an input buffer area, 43 is a basic transfer lock decoding unit,
44 is a timing generation circuit, 45 is a (view-report area address buffer, 46 is an address switching circuit, 47 is another RAM information area, 48 is a data bus switching circuit, 49 is an internal data bus, and 50 is an internal address bus. be.

Next, the internal operation will be described. First of all, CPUAC
From (J), 7 pulses are used as a leader clock for each CP.
Sent to U. During this time, each CPU in C2 sets the "all" information in the other RAM information area u1 to the output buffer area.Next, if the number of data bits is 8 bits, each data information is serially sent to the CPU in synchronization with the basic clock.
will be forwarded to. As shown in Figure 4 (a.
(I) 12 is inputted into the input buffer area by CPUC (8 pits of data from 1).

The next 7 clocks are saved as internal processing time.

In the meantime, the data input to the input buffer area (4B) is transferred in parallel to the output buffer area via the data bus switching circuit (481) and the timing ordering circuit via the internal data bus switching circuit (48). (Other RAM information area according to timing 1c of 44I (II of 4η)
bII.

Thereafter, in the same manner as above, the next 8 pits of serial data are transferred in synchronization with the basic clock.

1? The contents of each CPU's RAM information area +471 after 2f cycles are shown in FIGS. 4(a) and 4(bl).

In this case, since there are 3 CPUs, the value of the address buffer is initialized after 2 cycles, and the same cycle is repeated thereafter. As described above, with this system configuration, the latest other CPU information can always be easily obtained in the other RAM information area (47).

Since this system shares an internal address bus and an internal data bus, path control is performed by the timing generation circuit 4, and when another RAM information area 7 is being accessed, a wait time is applied to normal RAM access. This prevents overlapping of path data. As an extension of this system, as shown in Figure 6 (2), by using a clock whose phase is shifted by 180 degrees from the CPU's system basic clock as the transfer basic clock, there is no RAM weight.
(It goes without saying that transfer between the RAM information area, the output buffer 1, and the input buffer 2 is possible.

Further, by giving an initial offset to the address pointer for each CPU in the address of the other RAM information area, it is possible to set the transfer data to a common address value among the CPUs.

Also, by adding address data to the transfer data format, the transfer order can be input and output at random instead of sequentially, and the other RAM area can also be used as a common RAM area, and the address pointer can be set arbitrarily. It is also possible to send data faster than before.

In the transfer 1 word, the data signals are synchronized with the basic clock, but if the clock deviates, data will be erroneously determined. Therefore, the same J41J aha maintenance rule.
I need a song. The transfer waveforms are shown in Figures 7 and 8. The Y section river is the section for synchronization adjustment, and data 1. (The section where the signal is 0" and the synchronization signal is "Engine" is longer than a certain period fJ [
The time when the data transfer starts is detected as the start of data transfer.

If the basic clock is 4 MHz, one period '1' = 25
0 nsec and using 3 CPUs °C
Assuming 1 address is 12 bits and data is 8 bits, WA
1 for one round of data transfer with 2μsec between
It will take 015 μsec x 3 = 31.5 μsec.

As a 6-inch controller, it is on the order of several 10m5ec, and even when a data transfer error occurs, it takes 31.5μsec.
There is no particular problem as it will be corrected later. Depending on the purpose of handling, it is necessary to review the basic clock. To prevent malfunctions, perform multi-point reading, and if they match, consider it as normal data, or use a transfer clock.
Of course, it is also possible to reduce the time taken by the influence of misjudgment.

It is also easily possible to use the address part of the transfer waveform as a control command to control the CPU itself.

〔Effect of the invention〕

In view of the above, according to the present invention, information transfer between multiple CPUs can be achieved in a hardware-like manner (with an easy configuration, without any burden on the program, in the same way as regular RAM access). An information transfer system between CPUs can be provided.

[Brief explanation of the drawing]

Figures 1 and 2 C are diagrams for explaining conventional information transfer systems, Figure 3 is an external connection diagram of a system according to an embodiment of the present invention, and Figure 4 shows the contents of the 7111 RAM information area. The fifth factor is a functional block diagram inside the CPU, FIG. 6) is a phase relationship diagram between the CPU system clock and the transfer basic clock, and FIG. 7 is a transfer synchronization clock and data waveform diagram. FIG. 8 is a transfer synchronization clock and data waveform diagram when address data is added. 31.32.33...CPU 41...Output buffer area 42...Input buffer area 43...Transfer lock decoding section 44...Timing generation circuit 45...Other RAM information area address buffer 46・
...Address bus uJ 4-J circuit 47...fyaRA
M information area 48...Data bus disconnection circuit agent Patent attorney Nori Chika Kensuke (and 1 other person) Figure 1 Figure 2 Figure 8 Figure 4 Cp7A (A) Kui Figure 5 Figure 6 Ya vassal Lord Itt0ck Fig.

Claims (2)

[Claims] (1) Each of the multiple CPUs that transfer information has a RAM area for mutual transfer, 1-bit serial input, 1-bit serial output, and 1-bit basic clock input/output for synchronization that can be specified by a program. Set up a hotra,
An information transfer system for multiple CPUs, characterized in that information of other CPUs can be obtained in the same way as accessing internal RAMy. (2) Sending address information or command information and data information as a pair in a serial transfer signal I: Therefore, by changing the address information of mutual transfer RAM, RAM information can be transferred quickly. An information transfer system according to claim 1, characterized in that: