JPH0668022A - Direct memory access device - Google Patents

Abstract

PURPOSE:To execute the complicated discontinuous space DMA operation with a relatively simple logic and to relatively easily change the function. CONSTITUTION:A pair of buffer memories 13 and 14 are provided and are used like a toggle by an input-side DMAC and an output-side DMAC 12. That is, the input-side DMAC 11 stores designated data on a memory 1 in the first buffer memory 13; and when the first buffer memory 13 is filled up, the DMAC 11 stores data in the second buffer memory 14. The output-side DMAC 12 reads out data from the first buffer memory 13, where data is already written, to transfer this data to an input/output device 3 while the input-side DMAC 11 writes data in the second buffer memory 14. Since each of DMACs 11 and 12 executes only the fundamental operation without the data read after write processing to buffer memories, the logic constitution is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access device suitable for transferring data stored in a discontinuous space on a memory.

[0002]

2. Description of the Related Art Direct memory access (DMA) devices reduce the load on the data processing of the processor,
It is widely used in computers for speeding up processing. FIG. 2 is a diagram for explaining the basic operation of a conventional general DMA. First, a general DMA operation will be described with reference to this figure. In the figure, the memory 1 is a data transfer source,
A configuration for transferring data to the input / output device 3 of the transfer destination by using the direct memory access controller 2 is illustrated. The memory 1 is, for example, a main storage device of a computer, and the input / output device 3 is an I / O device such as a magnetic disk device. Direct memory access controller 2
Receives a notification of the start address 5 and the data amount 6 from the processor, reads the data 4 stored in the memory 1 and transfers it to the input / output device 3. Although the above operation is the most basic operation, data is not always continuously stored in the memory 1. Therefore, a direct memory access request for the data stored in the discontinuous space on the memory 1 may occur.

FIG. 3 is an explanatory diagram of a conventional discontinuous space DMA operation corresponding to such a case. This figure is also memory 1
3 illustrates a configuration for transferring data to the input / output device 3 by using the direct memory access controller 8. In the memory 1, for example, data 4-1 in three areas,
4-2 and 4-3 are stored. These areas are
They are separated from each other at completely different places, and the direct memory access controller 8 sends the head addresses 5-1 and 5- of the respective data 4-1, 4-2 and 4-3 from the processor to the direct memory access controller 8.
2, 5-3 and data amounts 6-1, 6-2, 6-3 are notified.

In such a case, a buffer memory 9 is provided in advance in the direct memory access controller 8 in order to collectively transfer the read data to the input / output device 3. Then, the direct memory access controller 8 starts reading from the first data 4-1 and stores it in the buffer memory 9, then reads another data 4-2, transfers it to the next area of the buffer memory 9, and finally. The data transfer operation from the memory 1 to the buffer memory 9 is repeated such that the data 4-3 is read and transferred to the buffer memory 9. Then, after that, the transfer from the buffer memory 9 to the input / output device 3 is performed. This transfer is also controlled by the direct memory access controller 8.

[0005]

By the way, in the case of executing the discontinuous space DMA operation as described above, the direct memory access controller 8 performs a process of sequentially writing data in the buffer memory 9. Information indicating which data is currently being transferred, the write start address in the buffer memory 9,
The processing is executed while recognizing various other information.

On the other hand, the direct memory access controller 8 of this type is usually required to have a high speed, and is therefore constituted by hardware instead of software. That is,
When information such as the head address and the amount of data is stored in a predetermined register from the processor, the logic such as the counter and the logic gate group that constitute the direct memory access controller 8 operates to automatically perform the data transfer.
Therefore, compared with the basic direct memory access operation as shown in FIG. 2, the discontinuous space D as shown in FIG.
The direct memory access controller 8 for executing the MA operation requires very complicated logic. In addition, the processor has a basic operation and a discontinuous space DMA.
Two types of logic must be prepared when both operations may be required. Furthermore, when changing such a transfer operation, it becomes necessary to reconstruct the logic. As described above, the conventional DMA device has a drawback that it is a heavy burden in terms of cost and maintenance in terms of circuit cost and maintenance management thereof.

The present invention has been made by paying attention to the above points, and a complicated discontinuous space D can be formed by a relatively simple logic.
It is an object of the present invention to provide a direct memory access device that can execute MA operation and can relatively easily change its function.

[0008]

The direct memory access device of the present invention comprises a pair of capacities that are ½ or less of the average transfer amount of the data amount to be transferred when a direct memory access request is received from the transfer source. The 2-port type buffer memory, the input side direct memory access controller for transferring data from the transfer source to one buffer memory, and the data already stored by the immediately preceding transfer operation from the other buffer memory for the input side direct memory access controller. An output side direct memory access controller for transferring to the transfer destination in parallel with the transfer operation of the memory access controller is provided. Further, a random access memory for storing parameters including a plurality of read addresses and a data amount at the transfer data transfer source, and a processor for controlling rewriting of the parameters stored in the random access memory are provided. It is characterized by that.

[0009]

This device is provided with a pair of buffer memories, which are connected to the input side direct memory access controller (D
It is used as a toggle between the MAC) and the output side DMAC. That is, the input side DMAC stores the designated data in the memory in the first buffer memory, and stores the data in the second buffer memory when the first buffer memory becomes full. The output-side DMAC reads the data from the first buffer memory in which the data has already been written and transfers it to the input / output device while the input-side DMAC is writing the data in the second buffer memory. The additional data writing process to the buffer memory is not performed, and each DMAC executes only the basic operation, which simplifies the logic configuration. When the transfer of continuous data to the buffer memory is completed, the start address and data amount of the next area are recognized, and the buffer memory to write the data is also switched. Therefore,
Even if the space storing the read data is switched,
The operation of the input side DMAC does not change. The operation of the output side DMAC is similar. By changing the switching timing parameter of such a toggle operation, it is possible to change the direct memory access operation without changing the logic.

[0010]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a direct memory access device of the present invention. In the figure,
This device is configured to transfer data from a transfer source memory 1 including a main storage device of a computer to a transfer destination input / output device 3 connected to a magnetic disk device or the like. . An input side direct memory access controller 11 is provided on the memory 1 side, and an output side direct memory access controller 12 is provided on the input / output device 3 side. A pair of buffer memories, that is, a first buffer memory 13 and a second buffer memory 14 are provided between them. Input side direct memory access controller 11 and a pair of buffer memories 13,
The selectors 15 are connected between the fourteen.

A selector 16 connects the output side direct memory access controller 12 and the pair of buffer memories 13 and 14. These selectors 15 and 16 connect the second buffer memory 14 to the output side direct memory access controller 12, for example, when the first buffer memory 13 is connected to the input side direct memory access controller 11, and at the next timing, The second buffer memory 14 is connected to the input side direct memory access controller 11, and the first buffer memory 13 is connected to the output side direct memory access controller 12. Such a switching operation has been widely used for continuous high-speed data transfer in the related art, and a description of its control circuit will be omitted. In the present invention, the pair of buffer memories 13 and 14 are used as toggles in this way to simplify the transfer operation.

FIG. 4 is an explanatory diagram of the average transfer amount for determining the capacities of the first buffer memory 13 and the second buffer memory 14 described above. As shown in the figure, in the system shown in FIG. 1, the vertical axis indicates the number of direct memory access requests,
When the statistics are shown with the horizontal axis representing the amount of data transferred for each request, an appropriate distribution centered on the average transfer amount M is obtained. In the case of the device of the present invention, the capacities of the first buffer memory 13 and the second buffer memory 14 are selected to be about one half of the average transfer amount, where M is the average transfer amount.
Therefore, if an average data transfer request is made, the first
Data transfer is carried out by fully using the buffer memory 13 and the second buffer memory 14. As described above, basically, in the present invention, additional data is not added to the buffer memory. In other words, if the buffer memory capacity is too large, the unused portion increases and resources are wasted. On the other hand, if the capacity of the buffer memory is too small, the number of times of toggle switching, which will be described later, increases, and the data transfer time becomes long as a whole. In consideration of these points, the capacity of the buffer memory is determined as described above.

Referring back to FIG. 1, the schematic operation of the apparatus of the present invention will be described with reference to this figure. In the input side direct memory access controller 11, the start addresses 5-1, 5-2, 5-3 of the data 4-1, 4-2, 4-3 stored in the memory 1 from the processor and the data amount 6 are stored. -1,
6-2 and 6-3 are notified. Further, in the device of the present invention, the input side direct memory access controller 11 and the output side direct memory access controller 1
The parameter for the toggle switching timing for 2 is notified. This parameter is actually used as an initial value of a counter that counts the amount of read data, and the first buffer memory 13 and the second buffer memory 1 are used.
When data is written up to the full capacity of 4,
A switching signal is output from the counter to the selectors 15 and 16 and is used for control such that the data transfer destination is switched. Therefore, the head address, the amount of data, the toggle switching timing parameter 17 and the like shown in the figure are stored in the memory or the like in advance, but the others are all configured by logic.

That is, for the first data 4-1,
The direct memory access controller 11 starts the operation of transferring to the first buffer memory 13. When the first buffer memory 13 is full, the selector 1
5 is switched. When the selector 15 is switched, the remaining portion of the data 4-1 is stored in the second buffer memory 14 this time. At this time, the first buffer memory 1
3 and output side direct memory access controller 12
Are connected by the selector 16, and the output side direct memory access controller 12 reads the already stored data from the first buffer memory 13 and transfers it to the input / output device 3.

The capacities of the first buffer memory 13 and the second buffer memory 14 are, as described above, the data 4-1.
Is an average amount, it is selected to be about half or less of the average amount. Therefore, the data transfer is completed by repeating the above operation several times. Then, when the last data of the data 4-1 is written in the second buffer memory 14, for example, the operation is temporarily stopped even if the second buffer memory 14 is not full. And the selector 15,
16 is switched, and the process for transferring the data 4-2 is started this time. The data 4-2 is newly started to be transferred to the first buffer memory 13. Therefore, the subsequent operation is exactly the same as the first data 4-1 transfer operation. Therefore, neither the input-side direct memory access controller 11 nor the output-side direct memory access controller 12 need to perform any control for complicated additional write processing, which has been conventionally performed.

FIG. 5 is a block diagram of the essential parts of a specific example showing the apparatus of the present invention in more detail. The device of the present invention is specifically implemented, for example, in such a configuration. This device
Data is transferred from a transfer source main storage device (not shown) connected to the main bus 21 to a transfer destination magnetic disk device (not shown) connected to the I / O bus 22. The device is provided with an internal bus 23, and a microprocessor 24 connected thereto controls the operation of the entire device. A main bus interface unit 25 is provided between the main bus 21 and the internal bus 23, and the main bus DMA controller 26 transfers data to the data buffer 27 via the main bus interface unit 25.
The configuration is such that the direct memory access operation is executed in the manner described above.

An I / O bus interface unit 29 is provided between the internal bus 23 and the I / O bus 22 to transfer the data stored in the data buffer 27 to the I / O bus 22.
I / O bus DMA controller 2 for transfer to
8 are provided. Further, a storage device 32 is provided for storing the above-described start address, data amount, toggle switching timing parameter, and the like. Further, a read-only storage device 31 is provided for controlling the operation of the microprocessor 24.

FIG. 6 shows the data buffer 27 shown in FIG.
2 is a block diagram of a main part showing a specific configuration of FIG. This data buffer 27 is provided with a total of n sets of buffer memories each composed of two sets. DMA channel 0
Buffer A side 27-01 and DMA channel 0 buffer B side 27-02 form a set and are used for the transfer operation as described above with reference to FIG. The other part, DM
The buffer A side 27-11 for A channel 1 and the buffer B side 27-12 for DMA channel 1 constitute a buffer memory for another channel. The buffer memory for the other channels is configured by one set up to the buffer B side 27-n2 for the DMA channel n. As described above, in the actual example, one set of buffer memories is provided for each of a plurality of channels of the input / output device, and the direct memory access operation can be independently performed.

In the apparatus of FIG. 5, when the operation is started, a direct memory access request is input to the microprocessor 24 through the main bus 21 and the main bus interface section 25, and the head address is further passed through the same route. And the amount of data to enter. These input information are stored in the storage device 32. After that, the microprocessor 24 generates the toggle switching timing parameter according to the program for the predetermined operation start processing stored in the read-only storage device 31, and the main bus DM
It is stored in a predetermined register of the A controller 26 or the I / O bus DMA controller 28. Also, the parameters for controlling the operation timing of the I / O bus DMA controller 28 are notified at the same time. Then, as described above when the operation start instruction is given, the main bus DMA controller 26 stores the data in one of the set of buffer memories provided in the data buffer 27, and in parallel with this, the I / O The operation in which the bus DMA controller 28 reads data from the other buffer memory and transfers it to the I / O bus 22 is executed.

In the embodiment shown in FIG. 6, for example, the capacity of each buffer memory was selected to be about 2 kilobytes, and good results were obtained. Further, by changing the program stored in the read-only storage device shown in FIG. 5, it is possible to change the division method of the data buffer 27, the toggle switching timing generation method, and the like. In this case, there is no need to change the logic configuring the main bus DMA controller 26 or the I / O bus DMA controller 28. Further, in the method of the present invention, since the buffer memory is used as a toggle to perform the data transfer, the transfer speed thereof is not substantially reduced as compared with the conventional method.

By the way, as shown in FIG. 5, the data buffer 27 is connected to the main bus interface section 25 and the internal bus 23, and the main bus DMA controller 26 and the I / O bus DMA controller 28 are connected to the data buffer 27. Are simultaneously accessed to perform data transfer. Therefore, as the data buffer 27, a so-called 2-port memory that can be accessed simultaneously is used. This prevents the bus from being occupied while one of the direct memory access controllers is being accessed and the access of the other direct memory access controller being prohibited.

The present invention is not limited to the above embodiments. The hardware configuring the device may be configured using various circuits having the schematic block configuration shown in FIG. In addition, the operation of dividing the data buffer to form some buffer memories and the processing of using the data buffer 27 as a whole to execute the basic operation are selectively used according to the request. Good.

[0023]

The direct memory access device of the present invention described above uses a pair of two-port type buffer memories each having a capacity equal to or less than one-half of the average data transfer amount as a toggle, so that the input side The direct memory access controller and the output side direct memory access controller are operated in parallel, respectively, and a complicated discontinuous space DMA operation or the like can be performed at high speed by a basic and simple logic. Moreover, since the parameters and the like can be easily changed by changing the program for the operation preparation, it becomes possible to control the complicated DMA operation without additional change of the logic.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a direct memory access device according to the present invention.

FIG. 2 is an explanatory diagram of a basic operation of a conventional general DMA.

FIG. 3 is an explanatory diagram of a conventional discontinuous space DMA operation.

FIG. 4 is an explanatory diagram of an average transfer amount.

FIG. 5 is a block diagram of a main part of a specific example of the apparatus of the present invention.

FIG. 6 is a block diagram of a main part of a data buffer of the device of the present invention.

[Explanation of symbols]

 1 memory (transfer source) 3 input / output device (transfer destination) 11 input side direct memory access controller 12 output side direct memory access controller 13 first buffer memory 14 second buffer memory 15, 16 selector

Claims (2)

[Claims] 1. A pair of two-port type buffer memories having a capacity equal to or less than ½ of an average transfer amount of data to be transferred when a direct memory access request is received from the transfer source; An input side direct memory access controller that transfers data to one buffer memory, and data that has already been stored by the previous transfer operation from the other buffer memory in parallel with the transfer operation of the input side direct memory access controller. A direct memory access device comprising an output side direct memory access controller for transferring to a transfer destination. 2. A random access memory that stores parameters including a plurality of read addresses and a data amount at a transfer source of transfer data, and a processor that controls rewriting of the parameters stored in the random access memory. The direct memory access device according to claim 1, further comprising: