JPS63226118A - Ad converter - Google Patents

Abstract

PURPOSE:To realize the titled converter by applying the mode setting of a sample-and-hold means, setting of a digital value of a DA conversion means and read of the output of a comparator means based on a program to generate a digital signal corresponding to the input analog signal. CONSTITUTION:If the AD conversion system is of the voltage V-pulse width T type, for example, the processing means sets the sample-and-hold circuit 1 to a 1st mode, where an input analog signal is sampled and held. Then the processing means sets a DA converter 8 to allow it to count up sequentially from '0', reads the output of a comparator 9 and outputs a set digital value when the result of sample-and-hold of the input analog output signal is equal to the analog value corresponding to the set digital value and the output value is changed as the result of the AD conversion. The processing means applies the similar processing every time an interruption signal is supplied from the timer 4. The desired AD conversion system is realized by one set of AD converter by having only to change the content (program) of the storage means (memory 5) in such a way.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an AD conversion device that converts an input analog signal to a digital signal, and particularly relates to an AD conversion device that can realize various AD conversion methods with one device. It is.

(Prior art) A of general-purpose AD conversion units, general-purpose AD conversion ICs, etc.
The AD conversion methods that have been put into practical use in D conversion devices include (a) counting method, (b) feedback comparison method, and (c)
) Non-feedback comparison method etc.

The counting method is a method in which an analog voltage is converted into a pulse train of a number proportional to its magnitude by some method, and AD conversion is performed by counting the number of pulses with a counting circuit.

Specific examples of this method include the V-T type, which performs the conversion operation using the linear relationship between the input terminal ■ and the pulse width T, and the V-T type, which performs the conversion operation using the linear relationship between the input terminal V and the pulse frequency F. There is a V-F type.

The feedback comparison method is a method that has a DA converter as a feedback circuit, and performs AD conversion by comparing the output voltage of the DA converter with the input terminal in the comparison circuit and operating so that the two become equal. Specific examples of this method include a successive approximation type in which the conversion operation is performed by successively comparing the input terminal V from the most significant bit of the binary number, and a type that uses the magnitude relationship between the previous value sample data and the current sample data. There is a follow-up comparison type that performs conversion operations.

The non-feedback comparison method is an AD conversion method that can generate a digital value at high speed through one comparison by having a plurality of voltage comparison circuits. A specific example of this method is a parallel comparison type that has voltage comparison circuits for each type of numerical value contained in the code and performs the conversion operation in one operation.

Comparing the above various methods in terms of conversion speed, in order to generate an n-bit digital number 15, the V-T type requires a maximum of 2° steps, the successive approximation type requires n steps, the tracking comparison type requires a maximum of 2n steps, and parallel One step conversion processing time is required for each type. Therefore, parallel type and successive approximation type are suitable for fields that require high-speed operation. Furthermore, when comparing the amount of circuit configuration for generating an n-bit digital signal, the parallel type is generally the most common type, followed by the successive approximation type, the tracking comparison type, and the VT type. In addition, regarding the conversion granularity, in general, except for the parallel type, the conversion granularity is about the same, and it can be said that the granularity is relatively high.

Therefore, when deciding the AD conversion method of the AD conversion device,
It is necessary to develop a method that takes into account the processing speed, accuracy, and amount of available circuitry necessary for the field of use.

Note that, as a specific example using the follow-up comparison type AD conversion method, there is a waveform storage device disclosed in, for example, Japanese Patent Laid-Open No. 60-25100.

(Problems to be Solved by the Invention) However, in the conventional AD conversion device, the conversion speed and the number of conversion bits are limited by the AD conversion adopted, so in order to change these, it is necessary to There is a problem in that an AD conversion device that adopts the AD conversion method must be used.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an AD converter that can be realized using the same circuit and a minimum circuit configuration.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an AD converter that converts an input analog signal into a digital signal and outputs the digital signal. 1 mode, and a second mode that outputs the input analog signal.
(b) DA conversion means for converting the set digital value into an analog signal; (C) comparison means for comparing the output values of the sample and hold means and the DA conversion means; (d) timer means for generating periodic interrupt signals; (e) voltage-pulse width type;
Storage means for storing a processing algorithm for a desired AD conversion method among various AD conversion methods including successive approximation type, tracking comparison type, and parallel type AD conversion methods; (f) an interrupt signal from the timer means and storage; Based on a processing algorithm stored in the means, a mode setting of the sample hold means, a digital value setting of the DA converting means, and an output value of the comparing means are performed to create a digital signal corresponding to the input analog signal. and processing means for performing processing.

(Function) According to the present invention, since the AD conversion device is configured as described above, the technical means functions as follows.

The processing means (for example, a microprocessor, a data register, etc.) sets the mode of the sample and hold means, and sets the digital value of the DA conversion means based on the interrupt signal and the processing algorithm of the desired AD conversion method, that is, the program stored in the storage means. setting and reading the output value of the comparison means to create a digital signal corresponding to the input analog signal.

For example, if the AD conversion method is a voltage (V)-pulse width (T) type, the processing means first sets the sample and hold means (for example, a sample and hold circuit and a setting register described later) to the first mode, Sample and hold the input analog signal. Next, the processing means sets the DA conversion means (for example, a register, a ladder resistance network, etc.) to count up sequentially from 0.0, reads the output value of the comparison means, and samples the input analog signal. When the hold result and the analog value corresponding to the set digital value become equal and the output value changes, the set digital value is output as the AD conversion result.The processing means performs similar processing when an interrupt signal from the timer means is input. Do it every time you are asked.

In this way, a desired AD conversion method can be realized with a single AD conversion device by simply changing the contents (program) of the storage means, so that the problems of the prior art described above can be solved.

(Embodiment) FIG. 1 is a block diagram of an AD conversion device showing a first embodiment of the present invention. In the same figure, 1 is a sample and Hall 1 circuit (S&H circuit), and the analog input signal 5GI
Used to temporarily hold N. Reference numeral 2 denotes a register (LVLREG) for controlling the operation of the sample and hole 1 circuit 1, and specifically controls whether the S&H circuit 1 is placed in the through mode or the sample mode. Reference numeral 3 denotes an arithmetic processing unit (LPU) such as a microprocessor, which operates according to an algorithm stored in a control memory, which will be described later.

LPt13 is an internal register and has -(L, PRA31 and LPRB32. 4 is an interval timer (TMR) for giving periodic interrupts to LPU3,
The AD conversion process is performed by periodic interrupt processing. 5 is a memory for storing processing algorithms (various AD conversion methods) for controlling the LPU 3, and 6 is a data register (DATA REG) for outputting AD-converted digital values to the outside. 7 is a register for the LPU3 to sense the level output from a comparator, which will be described later, and 8 is a DA converter (LDR), which is usually configured with a register, ladder resistance network, etc.
In order to improve the granularity of conversion, a constant current source driving circuit may be incorporated. Reference numeral 9 denotes a voltage comparator, which compares the output from the sample and Hall 1 circuit 1 (point [present]) and the output from the DA converter 8 (point ■) and inputs the result to a register.

The AD conversion device of this embodiment has an S&H circuit I and a register 2 for mode setting in addition to the configuration of the main part of the waveform storage device described above, so as to be compatible with various AD conversion methods described below.

Below, the operation of the AD converter of the first embodiment will be described as (a) V
- T type conversion operation, (b) successive approximation type conversion operation and (C)
The follow-up comparison type conversion operation will be explained separately.

(a) VT type conversion operation FIG. 2 is a flowchart showing a processing algorithm of the VT type AD conversion method stored in the memory 5. 3(a) and 3(b) are explanatory diagrams of operations when the processing algorithm shown in FIG. 2 is executed by the LPU 3. 3(a) shows operating waveforms, and FIG. 2(b) shows the output value (DOUT) of the data register 6.

The VT type conversion operation will be explained below with reference to FIGS. 2 and 3.

In response to periodic interrupts from the interval timer (TMR) 4, the LPU 3 executes the algorithm shown in FIG. When a timer interrupt occurs, LPI]3 sets register 2 to sample and hold mode. As a result, the analog input signal 5GIN is held, as shown in FIG. 3(a).
Maintain the level indicated by ■ (Sl). Next, the register (LPRA) 31 inside the LPU3 is cleared to O, and then the value of the LPRA31 is transferred to the LDR8, so “0°°” is input to one input terminal of the comparator 9 (S
2, 53a), then the output of the comparator 9 is sent to the register (L
VLREG) 7 and is read into the LPU3 (7) internal register (LPRB) 32 (S3b). Since the input terminal level of the comparator 9 at this point is in the relationship ■>[present], LP11B=1, and the loop processing shown in steps S3a to S3d is repeated. Through this loop processing, the value of one input terminal (■) of the comparator 9 is continuously multiplied and becomes a sawtooth wave, but when the voltage reaches 0=■, that is, the value of the internal register LP of LP01
When RB=0, the loop processing ends and the value of LPRA31 at that time is stored in the data register (DATA RE
G) Set to 6 (S4). That is, the value at that time is
This is 0111 (binary number) shown in FIG. 3(b). After that, reset register 2 from LP port 3 and perform one AD.
The conversion ends (S5).

By repeating the same process, the analog input signal 5GIN
From data register 6, 1011°1110
．． 1100 will be output at 7MR4 interrupt cycle ts intervals. Incidentally, one drawback of this method is that the AD conversion processing time tc varies depending on the amplitude of the analog input signal 5GIN. If the number of conversion bits is n bits, then 2
If the interrupt period ts is determined so that the relationship tc<ts is satisfied, the interrupt can be processed without any problems.

(b) Successive Approximation Type Conversion Operation FIG. 4 is a flowchart showing the processing algorithm of the successive approximation type AD conversion method stored in the memory 5. Fifth
Figures (a) and (b) show the processing algorithm in Figure 4.
FIG. 6 is an explanatory diagram of the operation when executed by P01. Same figure (
(a) shows the operating waveform, and (b) of the same figure shows the data register 6.
This shows the output value (DOUT) of.

The successive approximation conversion operation will be described below with reference to FIGS. 4 and 5.

According to periodic interrupts from 7MR4, LP01:
Execute the algorithm shown in FIG. When a timer interrupt occurs, LP01 sets register 2 to sample hold mode. As a result, the analog input signal 5GIN is held and maintains the level shown by ■ in FIG. 5(a) (Sll). Next, through the LPU 3, set the data register (DATA REG) 6 to "0°" and set the internal register (LPRA) 31 of the LP01.
The binary number 10000 is set in (S13). After completing the above initial settings, the internal register (LPRA) 3 of LP01
1 is transferred to LDR8 (S14a). In this embodiment, analog input signals SG1. N is 5 bits, i.e.
Since the processing is performed using 32 quantization steps, the analog voltage output from the LDR 8 is at the level shown in (1) in FIG. value. At this point, the level is sensed by register (LVL REG) 7 and the internal register (L
PRB) 32 (s14b). At this time, ■〉■
Therefore, LPRB=0, and the MSB of data register 6, ie, the 5th bit, remains 0, and then the process of the 4th bit is executed (S14c). In order to process the 4th bit, first set the initial setting of LPRA.
=10000 (binary number) is logically shifted to the right by 1 bit (S14e, 5I4f), then LPRA=01
000 (binary number) is set in LDR8, and at this point the contents of register 7 are transferred to the internal register of LP01 (LDR8).
PRB) 32 (S14a, 514b)
. At this time, since the relationship is ■<■, LPR8=3, and the fourth bit of the data register 6 is set to "1" (S14d). Similarly, data register 6-3
The 1st bit, 2nd bit, and 1st bit are processed to finally generate DATA REG=01110 (binary number). To determine the end of one AD conversion, LP01
This is done when the internal register (LPRA) 31 of LPRA is logically shifted to the right and becomes "O" (S14f). LPR
When A=O, register 2 is set to through mode (that is, S&H mode is reset) and one AD conversion process is completed (515).

By repeating the same process, the analog input signal 5GIH
From data register 6, 10100°101
10 will be output at the interrupt cycle ts interval of 7MR4. Note that the AD conversion processing time of this method is based on the number of conversion bits n
In the case of bits, if the interrupt period ts is determined so that the relationship n - tc<ts is satisfied, processing can be performed without any problem.

(C) Follow-up comparison type conversion operation FIGS. 6(a) and 6(b) are flowcharts showing the processing algorithm of the follow-up comparison type AD conversion method stored in the memory 5, and FIG. 6(a) shows the initial setting process. , the same figure (b
) indicates the process after the initial setting process. Also the 7th
Figures (a) and (b) show the processing algorithm in Figure 6.
This is an explanatory diagram of the operation when executed by P01, in which (a) shows the operating waveform and (b) shows the output value (DOUT) of the data register 6. The following comparison type conversion operation will be described below with reference to FIGS. 6 and 7.

The follow-up comparison type conversion operation normally generates a 1-bit code from the difference value between the previous sample value and the current sample value.

Currently used methods include DPCM method, ADP
Although there are various tracking comparison types such as the GM method, in the case of this embodiment, the operation of the single delta modulation type, which is the most basic method, will be described.

The follow-up comparison type is a method in which the AD conversion operation is performed by only comparing the previous sample value and the current sample value in one step, so a sample and hold circuit is not required. Therefore, during the initial setting operation, register 2 is reset and set to through mode (S21). Further, the LDR8 is also set to 0'' via the internal register (LPRA) 31 of the LPU3 ((S22)).

Next, when a periodic interrupt is input from interval timer (TMR) 4 to LPU3, register (LVL REG)
The value 7 is read into the internal register (LPRB) 32 of the LPU 3 (S24). At this point, the analog input signal 5GIN=■ is compared with the previous sample value, ie, ■ (525a).

If the comparison result is LPRB=1, that is, ■>■, then LP
Increment RA31 and read the data register (DAT).
At the same time as outputting code “1” to AREG) 6, LP
Reset the value of RA31 to LDR8 (S26a, 52
7a, 528a). On the other hand, the comparison result is LPRB=O1
That is, if ■<■, LPRA31 is decremented and data register (DATAREG) 6 is set to code “0.”
” and at the same time output the value of LPRA31 to LDR20.
8 (S26b, 527b, 528).

The above-described operation is performed by interrupting the LP from TMR4.
By turning around within the interrupt processing routine of U3, the output of LDR8, ie, ■, operates as if it always follows analog input signal 5GIN=A.

The 1-bit code generated from the data register 6 at this time is as shown in FIG. 7(b).

FIG. 8 is a block diagram of an AD conversion device showing a second embodiment of the present invention. In this figure, the same reference numerals as in FIG. 1 indicate the same components. The difference from FIG. 1 is that in order to perform a parallel conversion operation, a plurality of registers 7, LDR 8, and comparator 9 are provided among the components shown in FIG. be. In this embodiment, in order to configure a 4-bit parallel AD converter, LDR(1) 801 to LD are used as LDR8a.
R(15)815, comparator (CI) as comparator 9a
There are 15 each of comparators 901 to 915, and the register 7a is configured to be able to detect the output levels of the comparators 901 to 915.

9(a) and 9(b) are flowcharts showing the processing algorithm of the parallel AD conversion method stored in the memory 5, in which FIG. 9(a) shows the flowchart during initial setting processing; b) shows the process after the initial setting process. 10(a) and 10(b) are explanatory diagrams of the operation when the processing algorithm of FIG. 9 is executed by LPU 3. FIG. This shows the output value (DOUT) of No. 6.

FIG. 11 is a diagram showing a data conversion table in the memory 5.

The parallel conversion operation will be described below with reference to FIGS. 9 to 11.

In the parallel type conversion operation, the sample and hold circuit 1 is not necessary because the AD conversion operation is performed by only one step of comparison, similar to the follow-up comparison type of the first embodiment. Therefore, during the initial setting operation, register 2 is set to through mode so that the analog input signal is directly transmitted to the comparators 901 to 901.
915 to be input (S31)
. In addition, 15 LDR type DA converters 801 to 81
5 is initialized from quantization level 1 to quantization level 15 (S32).

After the initial settings are completed, when an interrupt from TMR4 enters LPU 3, first register (LVL REG) 7 (7) contents (1
5 hits) to LP [J 3 internal register (LPRB)
32 (S33). Next, a table search is performed for the read 15-bit LPR 832 value using the data conversion table (FIG. 11) inside the memory 5 (S34). The first AD in Figure 10(a)
In the conversion operation, LPRB=(111110000000
000), so TBLOUT=(1010)
, that is, the value of 5 (decimal) is searched in the table and set in data register (DATA REG) 6 (
S35).

By repeating the same process, the analog input signal 5GIN
From data register 6, 1010°1110
．． 1100 will be output at TMR4 interrupt cycle ts intervals.

As described above, by configuring the AD conversion device as in the second embodiment, parallel conversion operation becomes possible, and furthermore,
By using a desired system among the LDR 8a, the comparator 98, and the register 7a, (a) VT type conversion operation, (b) successive approximation type conversion operation, and (C) described in the first embodiment can be performed. A follow-up comparison type conversion operation can also be realized in the same way.

As described above, according to the present embodiment, (1) only by changing the microprogram that controls the arithmetic processing unit 3, a general-purpose AD conversion method that is currently in practical use (a) VT type conversion method; (b) Successive approximation conversion method, (C) follow-up comparison conversion method, and (d) parallel conversion method can be realized. Therefore, the conversion speed and number of conversion bits of the AD conversion device can be adjusted simply by changing the microprogram, so the user can create a microprogram to achieve the conversion method, conversion speed, and number of conversion bits that suit the purpose of use. If you create it, you can immediately achieve the desired A.
Can be used as a D conversion device.

(2) The components of the AD conversion device of this embodiment are an arithmetic processing unit 3 and input/output registers 6.7 (7a).

Comparator 9 (9a), DA converter 8 (8a) including a ladder resistance network, sample and hold circuit 1, etc., so by converting the AD converter into an LSI, it becomes possible to configure a general-purpose AD converter element. . Therefore, by simply changing the microprogram inside the hydraulic LSI, an AD conversion element suitable for the purpose of use can be configured.

(3) In addition to the various AD conversion methods (a) to (b) explained above, by adopting the device of the present invention, it is possible to realize a considerable part of processing algorithms such as the DPGMPCM method) PCM method, so AD conversion It can be used not only as a system but also as an analog interface for digital signal processing such as digital compression/expansion processing.

(4) The average execution time for one instruction in the arithmetic processing unit 3, which is a component of the AD conversion device of this embodiment, is 0.8 to 1.0 μs.
If a general-purpose microprocessor such as ec is used, and the conversion bit length is 8 bits, the processing time for one AD conversion is 20 to 30 μsec for the successive approximation type and 2 to 5 μsec for the tracking type.
sec, it will be about 5 to 20 μsec in parallel type, so
It can be directly adopted in audio signal processing devices such as speech recognition and speech agreement.

(Effects of the Invention) As described above in detail, according to the present invention, various AD conversion methods can be realized with a single device with a simple circuit configuration by simply changing the contents of the storage means, that is, the program. At the same time, the conversion speed, number of conversion bits, etc. can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an AD conversion device showing a first embodiment of the present invention, FIG. 2 is a flowchart during V-T type conversion operation,
Figures 3 (a) and (b) are explanatory diagrams of VT type conversion operation, Figure 4 is a flowchart during successive approximation type conversion operation, and Figures 5 (a) and (b) are successive approximation type conversion operation. FIGS. 6(a) and 6(b) are flowcharts of the follow-up comparison type conversion operation, FIGS. 7(a) and (b) are explanatory diagrams of the follow-up comparison type conversion operation, and FIG. 8 is a flowchart of the follow-up comparison type conversion operation. 9(a) and (b) are flowcharts of the parallel conversion operation; FIGS. 10(a) and (b) are explanatory diagrams of the parallel conversion operation; The figure shows a data conversion table. ■...Sample and hold (S&H) circuit, 2.7 (7
a)...Register, 3...Arithmetic processing unit (LPU), 5...Memory 6...Data register (DATA REG). 8 (8a), 801 to 815 = JA conversion unit (CI) R
), 9(9a), 901-915--Comparators. 31.32...Internal register.

Claims (1)

[Claims] An AD converter that converts an input analog signal into a digital signal and outputs the digital signal, comprising: (a) a first mode in which the input analog signal is sampled and held; and a second mode in which the input analog signal is output. (b) DA conversion means for converting the set digital value into an analog signal; (c) comparison means for comparing the output values of the sample and hold means and the DA conversion means; (d) periodic timer means for generating an interrupt signal (e
) a storage means for storing a processing algorithm for a desired AD conversion method among various AD conversion methods including voltage-pulse width type, successive approximation type, tracking comparison type, and parallel type AD conversion methods; (f) the timer; Based on the interrupt signal from the means and the processing algorithm stored in the storage means, the mode setting of the sample and hold means, the setting of the digital value of the DA converting means, and the reading of the output value of the comparing means are carried out to convert the input analog A, characterized in that it comprises a processing means for performing processing to create a digital signal corresponding to the signal.
D conversion device.