JP2010033311A - Communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication system allowing an application to periodically carry out processing without being influenced by the case where another application causes a device driver to carry out processing that requires a processing time when the application periodically carries out a series of processing including an operating system and the device driver. <P>SOLUTION: The communication system for carrying out a first process 13a required to be periodically carried out at predetermined time intervals, and at least one of low-order processes 13b, 13c lower in priority than the first process, is provided with a process completion time measuring means for measuring the completion time of the low-order process when the low-order process is carried out for the first time, and storing the measured completion time, and a comparing means for comparing the completion time of the low-order process with a predetermined time set by the process completion time measuring means. If the completion time of the low-order process is longer than the predetermined time, the comparing means terminates the low-order process after the lapse of a fixed time equal to or shorter than the predetermined time from the state of executing the low-order process from the next time onward. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a communication system in which an analog signal input from an input terminal is converted into a digital signal, and a digital signal carried via a network is converted into an analog signal at an output terminal and output.

  In VoIP communication, a voice waveform picked up by a microphone as an input terminal, a voice signal from an oscillator or a CD (Compact Disk) is input as a continuous analog signal to a DSP (Digital Signal Processor), and is temporally changed. The signal magnitude is sampled at a constant interval Ts and converted into a discrete signal. The digitized digital data is encoded by being converted into a digital jumping numerical value that is discretized at a certain sampling period. It should be noted that how fine the level of a wave obtained by discretizing an analog signal at a certain sampling period can be quantized is determined by the number of bits used in A / D conversion.

  The encoded data is transferred to a CPU board having a CPU (Central Processing Unit). A predetermined operating system is mounted on the CPU board in order to perform more complex control or to perform various communication with various external interfaces. Under the management of the operating system, an application Converts the encoded voice information data from the DSP into an IP packet and sends it over the network.

  Encoded digital data transmitted from the DSP to the CPU is transmitted via an interface medium such as DPRAM, for example. When transmitted via DPRAM, audio information data is written from the DSP to the DPRAM. The CPU reads the voice information data written in the DPRAM and converts the voice information data into IP packets.

  The IP packet sent over the network is received by the VoIP output terminal and is compounded by the same method as the method encoded by the DSP, and the compounded data is restored to a continuous analog signal such as a voltage value. Is done. The restored analog signal is output from the VoIP output terminal as an audio signal.

  In converting the digitized and encoded voice data into IP packets, the encoding scheme G. 711 (PCM method: PCM = pulse code modulation, sampling frequency: 8 kHz, information amount: 64 kbps / channel, principle delay: 0.125 msec, quality: MOS value 4.10), G.711. 729 (CS-ACELP system: Conjugate Structure Algebraic Code Excited Linear Prediction, sampling frequency: 8 kHz, information amount: 8 kbps / channel, frame length: 10 msec, principle delay: 15 msec, quality: 3.9 in MOS value), etc. Encoding scheme G. 711, G.G. 729 is based on the premise that voice is packetized and transmitted over the network at a cycle of 20 ms. This means that the period in which the data encoded from the DSP is IP packetized by the CPU and sent over the network is 20 ms. It is possible to temporarily change the period of 20 ms.

  In a case where a series of processes in which encoded data sent from the DSP is converted into IP packets by the CPU and sent to the network are processed by a CPU board on which a predetermined operating system is mounted, an application, an operating system The device driver needs to perform a series of these processes.

  Under the instruction from the application, the device driver reads the encoded data from the interface device with the DSP via the operating system, delivers the data to the application, and processes the IP packetization by the application. The device driver sends a packet to the network again via the operating system.

  At this time, in a normal operating system, even if the processing time of the device driver is long, the control does not return to the application until the processing is completely completed. Therefore, the application periodically sends voice packets to the network at intervals of 20 ms. Even if it is programmed to be sent out, if the processing time of the device driver including the operating system does not operate within the allowable range for the application, the set time of 20 ms cannot be maintained. .

  If the processing of the device driver takes too much time, there is a possibility that the flow from the encoded data to the IP packetization may occur, and the operation of other applications may be affected.

  A communication system using VoIP communication is disclosed in Patent Document 1.

JP 2007-228461 A

  In view of such circumstances, the present invention periodically executes a series of processes including an operating system and a device driver, even when a process that requires processing time is executed from another application to the device driver. It is an object of the present invention to provide a communication system that can execute processing periodically without being affected by the previous application.

  The present invention is a communication system that executes a first process that needs to be periodically executed at predetermined time intervals and at least one lower process having a lower priority than the first process, the lower process A process completion time measuring means for measuring the completion time of the lower-level process at the first execution of the process, and storing the measured completion time, and a comparison means for comparing with a predetermined time set by the process completion time measurement means, If the completion time of the lower process is longer than a predetermined time, the comparison means ends the lower process after a predetermined time that is the same as the predetermined time from the start of the execution of the lower process, or shorter than the predetermined time. The present invention relates to a communication system.

  According to the present invention, there is provided a communication system that executes a first process that needs to be periodically executed at predetermined time intervals and at least one lower process having a lower priority than the first process, A process completion time measuring means for measuring a completion time of the lower process at the first execution time of the lower process and storing the measured completion time; and a comparing means for comparing with a predetermined time set by the process completion time measurement means If the completion time of the lower process is longer than a predetermined time, the comparing means will perform the lower process after the elapse of a fixed time that is the same as the predetermined time from the start of the execution of the lower process or shorter than the predetermined time. Therefore, even if the processing time of the lower process is longer than a predetermined time, the first process may be affected by the lower process. Without also possible to realize the execution of periodic treatment with simple modification.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a communication system according to the present invention.

  In the system shown in FIG. 1, an oscillator 1 as an input terminal outputs an analog signal 2 to a DSP board 3, and the DSP board 3 is connected to a CPU board 5 on which a CPU is mounted via an internal bus 4. 5 is connected to the network 7 by the Ethernet (registered trademark) 6 and connected to the output terminal 8 through the network 7.

  The oscillator 1 outputs the audio waveform picked up from the microphone and the audio signal from the oscillator and the CD to the DSP board 3 as the voltage change, the analog signal 2, and the DSP board 3 is inputted. The analog signal 2 is converted into a digital signal, and the converted digital signal is encoded. The internal bus 4 is an interface for transmitting digital data encoded from the DSP board 3 to the CPU board 5 and transmitting parameter setting information from the CPU board 5 to the DSP board 3. The CPU board 5 converts the encoded data into an IP packet using RTP (real-time transport protocol RFC 1889 / RFC 3350), and outputs the packet as voice packet data.

  The voice packet data is transmitted to the network 7 via the Ethernet 6, and the voice packet data is transmitted to the output terminal 8 via the network 7. The output terminal 8 that has received the voice packet data is compounded by the same method as that encoded by the DSP board 3, and the combined data is restored to the continuous analog signal 2 such as a voltage value. Is done. Finally, the restored analog signal 2 is output as an audio signal from the output terminal 8, and communication is established.

  Next, referring to FIG. 2, data communication between the DSP board 3 and the CPU board 5 will be described.

  The DSP board 3 mainly includes an A / D conversion unit 9 that receives the analog signal 2, a signal processing unit 11 connected to the A / D conversion unit 9, and data processed by the signal processing unit 11. The DPRAM 12 has a function of storing and sending the data to the CPU board 5.

  The CPU board 5 includes a CPU and a storage unit, and the storage unit stores an application 13, an operating system 14, a device driver 15, a process completion time measurement program, and a predetermined time comparison program. The CPU, the storage unit, and the process completion time measurement program constitute completion time measuring means, and the CPU, the storage unit, and the predetermined time comparison program constitute comparison means. A signal from the DPRAM 12 is input from the internal bus 4 via the device driver 15, and the device driver 15 outputs a digital signal to the Ethernet 6.

  The analog signal 2 oscillated from the oscillator 1 is first sampled at a certain time interval Ts in order to digitize the analog signal 2 by the A / D conversion unit 9 and discrete. To a typical digital signal. In sampling, sampling is usually performed at a sampling frequency that is twice or more the maximum frequency included in the analog signal 2.

  After being converted into a digital signal by the A / D converter 9, the magnitudes of the respective waveforms discretized at fixed sampling periods are then quantized into digital jump values. Also, how fine the level of the wave can be quantized is determined by the number of bits used in the A / D conversion.

  The data quantized by the A / D conversion unit 9 is encoded by the signal processing unit 11. As an encoding method, G.I. 711, G.G. 729 etc.

  The digital data encoded by the signal processing unit 11 is stored in the DPRAM 12 once because it is IP packetized by the processing by the CPU board 5. The digital data stored in the DPRAM 12 is transmitted to the CPU board 5 via the internal bus 4 for IP packetization.

  The application 13 accesses the device driver 15 via the operating system 14 and receives digital data read by the device driver 15 through the internal bus 4. The application 13 uses RTP standardized by IETF as a protocol for carrying the stream in real time when the encoded digital data is converted into IP packets. The RTP packet includes an RTP header, and the RTP header includes information such as a payload type, a sequence number indicating the order of voice conversion, and a time stamp that is a transmission interval of the voice packet.

  The digital data encoded in the RTP header is added as a payload with an information amount corresponding to the time stamp, and is sent as an audio packet from the application 13 to the Ethernet 6 via the operating system 14 and the device driver 15. Is done.

  Next, referring to FIG. 3 and FIG. 4, the operation of the CPU board 5 and the processing flow of the device driver 15 for realizing periodic processing will be described.

  In the CPU board 5, in order to process the encoded digital data into voice packet data, or to change parameter settings for the DSP board 3, the processes 13a to 13c are executed by the operating system 14. It operates sequentially under management. When a plurality of voice packet data are handled at the same time, the number of processes increases according to the number handled.

  In addition, the process 13a includes the encoding method G. If the voice packetization work is to be executed under H.711, the process 13a performs a process that places a processing load on the device driver 15 accessed by the process 13b and the process 13c. Regardless, it must operate with a 20 ms period.

  However, since the process 13a to the process 13c cannot access the device driver 15 without going through the operating system 14, the process 13b and the process 13c have a processing load on the device driver 15. When the processing takes time and the processing time becomes long, the process 13a may not be able to operate at a cycle of 20 ms.

  In the present invention, even when a process with a heavy processing load is executed, the process completion time measurement means determines which process is performed so that the entire process period is one operation at a predetermined time period, for example, a 20 ms period. It is possible to measure whether it takes a certain amount of time, and to compare whether the measured time is longer or shorter than 20 ms by the comparison means, and allow the time that the process 13a as the first process takes for the processing. Determine whether or not.

  First, the first operation when the process 13b and the process 13c implement processing that places a processing load on the device driver 15 will be described.

  When the process 13b and the process 13c access the device driver 15, the time to be allowed by the application 13 (20 ms) is delivered as an argument. The device driver 15 records the current time before executing the process (STEP: 1). Next, it is determined whether a series of processes is the first time (STEP: 2). Since the actual processing time is unknown for the first time, access is made to the device such as writing or reading, and the processing is executed until the processing is completed (STEP: 3). After completion of STEP: 3, the time after the end of the process is acquired (STEP: 4), and the processing time is calculated from the difference from the time before the start of processing recorded in STEP: 1 (STEP: 5). STEP: The processing time calculated in 5 is compared with the allowable time delivered as an argument when accessing the device driver 15, and it is determined whether the processing time of the process 13b and the process 13c can be permitted by the application 13. Check (STEP: 6), and if the time has passed after the permissible time, it is managed in the device driver 15 for passing through a routine for releasing the CPU after processing for a certain time from the next time. The flag is set to ON (STEP: 7), and the process is completed.

  Next, the second and subsequent operations will be described in STEP: 7.

  Regarding the second and subsequent operations, whether or not it is the first time passes through STEP: 2, and next, whether the processing time of the process 13b and the process 13c needs to consider the allowable time of the application 13 (STEP: 8), and if it is not necessary to consider, the processing is continued as it is, and it is necessary to consider the allowable time of the application. That is, if the flag of STEP: 7 is set to ON, the processing is performed for a certain period of time. Then, unless the argument for turning off the flag for passing through the routine for releasing the CPU is handed over, branch at STEP: 8, access to the device such as writing or reading, and release the CPU after processing for a certain period of time. (STEP: 9) The processing is continued until all the steps are completed.

  Since the process 13a executes processing after either or both of the process 13b and the process 13c temporarily release the CPU, the operating system 14 has a function of changing the priority of each process. Have.

  By executing the above processing, the process 13b and the process 13c, which take processing time, temporarily release the CPU, and the process 13a can execute the processing. Therefore, the process 13a has a cycle of 20 ms. I can protect it.

  As described above, by executing the process of the device driver 15 in the present invention, the flow of the encoded digital data into the IP packet is not fluctuated, and the device driver 15 By taking too much time for processing, it becomes possible to perform communication without affecting the operation of other processes.

  Needless to say, the present invention is applicable not only to VoIP communication but also to a system that requires other periodic processing.

It is a block diagram of the communication system which shows embodiment of this invention. It is explanatory drawing which shows the communication structure between the DSP board and CPU board of this invention. It is explanatory drawing which shows operation | movement within the CPU board of this invention. It is a flowchart which shows the operation | movement process for implement | achieving the periodic process in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Oscillator 2 Analog signal 3 DSP board 5 CPU board 8 Output terminal 9 A / D conversion part 11 Signal processing part 12 DPRAM
13 Application 14 Operating System 15 Device Driver

Claims (1)

  A communication system that executes a first process that needs to be periodically executed at a predetermined time interval and at least one lower process having a lower priority than the first process, the first process being executed for the first time A process completion time measuring means for measuring the completion time of the subordinate process and storing the measured completion time; and a comparison means for comparing with a predetermined time set by the process completion time measuring means. If the completion time of the lower process is longer than a predetermined time, the lower process is terminated after the elapse of a fixed time that is the same as the predetermined time from the start of execution of the lower process or shorter than the predetermined time. A communication system.

Images