JPS63215080A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents
Nonvolatile semiconductor memory and manufacture thereofInfo
- Publication number
- JPS63215080A JPS63215080A JP62047731A JP4773187A JPS63215080A JP S63215080 A JPS63215080 A JP S63215080A JP 62047731 A JP62047731 A JP 62047731A JP 4773187 A JP4773187 A JP 4773187A JP S63215080 A JPS63215080 A JP S63215080A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- forming
- mobile ions
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 150000002500 ions Chemical class 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 3
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 230000009545 invasion Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は不揮発性半導体メモリ及びその製造方法く関す
るもので、特にEPROM (Erasable PR
OM)やEBPROM (Fflectrical E
rasable PROM)といったデバイスに用いら
れるものである。また他のデバイス例えばDRAM (
Dynamic RAM) 、 8RAM(8tati
c几AM)等においても、可動イオンの影響を極力排除
したい場合に用いることができる。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory and a method for manufacturing the same, and particularly relates to an EPROM (Erasable PR
OM) and EBPROM (Fflextrical E
It is used in devices such as rasable PROM). Other devices such as DRAM (
Dynamic RAM), 8RAM (8tati
It can also be used in cases where it is desired to eliminate the influence of mobile ions as much as possible in the case where the influence of mobile ions is to be eliminated as much as possible.
(従来の技術)
一般に不揮発性メモリにおいては、デバイス中にNtx
+等の可動イオンが存在すると、電荷保持特性の劣化や
セルトランジスタのスレッショルド電圧の不安定性を招
く。特に最近では、不揮発性メモリが様々な分野で使用
されるようになってきておシ、比較的温度の高い環境下
でも使用される場合がアシ、デバイス中の可動イオン量
は非常に小さく抑制する必要がある。従来技術では、一
般にウェハプロセス中にウェハに付着したNa は、ゲ
ッタ工程を通すことで不動化する。例えば後酸化膜を形
成後、その上部にPSG膜を堆積し高温処理を加えると
、付着していたNa がPSG膜中に取シ込まれて不動
化される。またこのPSG膜は外部からのNa+の侵入
を防ぐ。(Prior art) Generally, in non-volatile memory, Ntx is used in the device.
The presence of mobile ions such as + causes deterioration of charge retention characteristics and instability of the threshold voltage of the cell transistor. Especially recently, non-volatile memory has come to be used in various fields, and it is often used in relatively high temperature environments, so the amount of mobile ions in the device is suppressed to a very low level. There is a need. In the prior art, Na attached to the wafer during the wafer process is generally immobilized through a getter process. For example, after forming a post-oxidation film, if a PSG film is deposited on top of it and subjected to high-temperature treatment, the attached Na is incorporated into the PSG film and becomes immobilized. This PSG film also prevents Na+ from entering from the outside.
(発明が解決しようとする問題点)
しかしこの方法の場合、コンタクトホールからの可動イ
オンの侵入は防止できない。つ″!シ高高温ゲタ工程後
コンタクトホールを開口するが、第6図に示すようにN
a+が侵入するおそれがある。(Problems to be Solved by the Invention) However, in this method, invasion of mobile ions through the contact hole cannot be prevented. After the high-temperature gettering process, contact holes are opened, but as shown in Figure 6, N
There is a risk that a+ may invade.
第6図中1は半導体基板、2はメモリセル部、3はフロ
ーティングゲー)、4はコントロールケート、5は後酸
化膜、6はPSG膜、7はコンタクトホールである。し
かして後酸化膜5は、Na 等に対して全くバリアと
はならない。コンタクト開口後の後処理やAt等の金4
配線層形成工程で可動イオンが侵入するおそれがちシ、
かつその後高温工程が入らないため、可動イオンをゲッ
タリングできない。In FIG. 6, 1 is a semiconductor substrate, 2 is a memory cell portion, 3 is a floating gate), 4 is a control gate, 5 is a post-oxidation film, 6 is a PSG film, and 7 is a contact hole. Therefore, the post-oxidized film 5 does not act as a barrier against Na, etc. at all. Post-processing after contact opening and gold 4 such as At
There is a risk of mobile ions entering during the wiring layer formation process.
Moreover, since there is no high-temperature process after that, mobile ions cannot be gettered.
本発明は上記実情に鑑みてなされたもので、コンタクト
ホールからの可動イオンの侵入を防止し、高信頼性を有
する不運発注半導体メモリ及びその製造方法を提供する
ものである。The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a highly reliable semiconductor memory that prevents the invasion of mobile ions from contact holes, and a method for manufacturing the same.
[発明の構成]
(問題点を解決するための手段と作用)本発明は、半導
体基板に形成された不揮発性半導体メモリセルと、この
メモリセルを覆う1間絶fj&膜と、この絶縁膜に設け
られたコンタクトホールと、このコンタクトホールを通
る金属配線層と、この層と前記コンタクトホールの内壁
との間に設けられ5i02膜より正の可動イオンを通し
にぐい層とを具備したことを第1の特徴とする。また半
導体基板に不揮発性半導体メモリセルを形成する工程と
、前記メモリセルを覆う眉間絶縁膜を形成する工程と、
前記層間絶縁膜にコンタクトホールを形成する工程と、
前記コンタクトホールの内壁にSio□膜より正の可動
イオンを通しにくい層を形成する工程と、前記コンタク
トホールを通る金属配線層を形成する工程と、前記可動
イオンを通しにくい層を形成後、前記金属配線層を形成
する前に700℃以上の高温にする工程とを具備したこ
とを第2の特徴と−する。即ち本発明は、コンタクトホ
ールからの可動イオン(StO□膜よりも正の可動イオ
ン)の侵入を防止するため、コンタクトホールの側壁(
内壁)部に、可動イオンを通過させにくい膜を形成する
もので、コンタクトホール開口後、特に金属配線層形成
時に侵入してくる可動イオンをプロ、りするものである
。また可動イオンを通過させにくい膜を形成後、1度7
00℃以上の高温工程を通すと、コンタクトホール開口
後、可動イオンを通過させにくい膜を形成するまでに侵
入した可動イオンを層間絶縁J[(例えばPSG膜)中
にゲッタリングでき、更に効果が大きくなる。上記可動
イオンをプロ、りする膜としては、例えばSt、N4膜
がある。[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a non-volatile semiconductor memory cell formed on a semiconductor substrate, a single insulation film covering the memory cell, and a non-volatile semiconductor memory cell formed on a semiconductor substrate. A contact hole provided in the contact hole, a metal wiring layer passing through the contact hole, and a layer provided between this layer and the inner wall of the contact hole that allows more positive mobile ions to pass through than the 5i02 film. 1 feature. Further, a step of forming a nonvolatile semiconductor memory cell on a semiconductor substrate, a step of forming a glabella insulating film covering the memory cell,
forming a contact hole in the interlayer insulating film;
forming a layer on the inner wall of the contact hole that is more difficult for positive mobile ions to pass through than the Sio□ film; forming a metal wiring layer that passes through the contact hole; and after forming the layer that is more difficult for mobile ions to pass through; The second feature is that the method includes a step of increasing the temperature to 700° C. or higher before forming the metal wiring layer. That is, in the present invention, in order to prevent the invasion of mobile ions (mobile ions that are more positive than the StO□ film) from the contact hole, the side wall of the contact hole (
This method forms a film on the inner wall that makes it difficult for mobile ions to pass through, and prevents mobile ions that enter after the contact hole is opened, especially during the formation of the metal wiring layer. In addition, after forming a membrane that does not allow mobile ions to pass through,
If the process is carried out at a high temperature of 00°C or higher, the mobile ions that have entered the contact hole can be gettered into the interlayer insulation (e.g., PSG film) until a film is formed that is difficult for mobile ions to pass through, which further improves the effect. growing. Examples of the membrane that absorbs the mobile ions include St and N4 membranes.
(実施例)
以下図面を参照して本発明の一実施例を説明する。第1
図ないし第5図は同実施例の工程図でおるが、これは第
6図の場合と対応させたので、対応個所には同一符号を
用いて説明を省略し、特徴とする点の説明を行なう。ま
ず後酸化膜5を600X形成後、P8G膜6を約600
01堆積させる(第1図)。次に平坦化を兼ねて高温熱
処理を行ない、この時にデバイスプ゛ロセス中で取シ込
まれたNa 等の可動イオンはPSG膜6にゲッタリ
ングされる(第2図)。次にPSG膜6と後酸化膜5よ
りなる層間絶縁膜にフォトリノグラフィによりコンタク
トホール2を開口する(第3−)。次KNa+の侵入を
阻止するため、S i 、N4膜1ノを例えば500X
堆積する。なおコンタクトへの再拡散が必要であれば%
5s5N4膜堆積前にイオン注入を行っておくとよい。(Example) An example of the present invention will be described below with reference to the drawings. 1st
Figures 5 through 5 are process diagrams of the same embodiment, but since they correspond to the case in Figure 6, corresponding parts will be given the same reference numerals and explanations will be omitted, and the description of the characteristic points will be omitted. Let's do it. First, after forming the post-oxide film 5 at 600X, the P8G film 6 is formed at approximately 600X.
01 is deposited (Fig. 1). Next, high-temperature heat treatment is performed for planarization, and at this time, mobile ions such as Na that have been introduced during the device process are gettered into the PSG film 6 (FIG. 2). Next, a contact hole 2 is opened in the interlayer insulating film composed of the PSG film 6 and the post-oxidized film 5 by photolithography (3rd-). Next, in order to prevent the invasion of KNa+, the Si, N4 film was heated at 500X, for example.
accumulate. % if re-diffusion to contacts is necessary.
It is preferable to perform ion implantation before depositing the 5s5N4 film.
更にこれに900℃、30分−のアニールを加える。こ
の工程で、コンタクト開口後から8 i 3N4膜11
堆積時までに侵入した可動イオンが再びP8G膜6中へ
取シ込まれる(第4図)。Furthermore, annealing at 900° C. for 30 minutes is added to this. In this step, the 8 i 3N4 film 11 is removed from after the contact opening.
The mobile ions that have penetrated up to the time of deposition are taken into the P8G film 6 again (FIG. 4).
次に几IE(几aactlne Jon Etchin
g)によりコンタクトホール
みにS t 5N4膜11を残す。次にアルミニウム膜
12を堆積しかつパターニングすると、コンタクトホー
ルと配線層が完成するものである(第5図)。Next, 几IE (几aactlne Jon Etchin
By g), the S t 5N4 film 11 is left only in the contact hole. Next, an aluminum film 12 is deposited and patterned to complete the contact hole and wiring layer (FIG. 5).
上記実施例によれば、コンタクトホール開口後、特にA
t1lJ12の形成時に侵入してくる可動イオンを5t
3N4[7Jでプロ、りできる。ま念S ; 5N4膜
1)を形成後、1度700℃以上の高温工程を通すと、
コンタクト開口後、S t 5N、膜1ノを形成するま
でに侵入し九可動イオンをPSG膜6中にゲ。According to the above embodiment, after opening the contact hole, especially A
5t of mobile ions that invade during the formation of t1lJ12.
You can play professionally with 3N4[7J. After forming the 5N4 film 1), once it passes through a high temperature process of 700℃ or more,
After the contact is opened, S t 5N invades and generates nine mobile ions into the PSG film 6 until the film 1 is formed.
タリングでき、更に効果が犬きくなるものである。It can be used for a variety of purposes, and the effect is even more intense.
[発明の効果コ
以上説明した如く本発明によれば、本発明を用いて作成
した不揮発性メモリにおいては、ウェハ中の可動イオン
の量が、従来技術のものに比較して少なく、信頼性の高
いデバイスが得られるものである。[Effects of the Invention] As explained above, according to the present invention, in the nonvolatile memory produced using the present invention, the amount of mobile ions in the wafer is smaller than that of the conventional technology, and the reliability is improved. This results in a high quality device.
第1図ないし第5図は本発明の一実施例を説明するため
の工程図、第6図は従来の不揮発性メモリの断面図であ
る。
1・・・半導体基板、2・・・メモリセル部、5・・・
後酸化膜、6・・・PSG膜、7・・・コンタクトホー
ル、1)・・・S s 5N4膜、12・・・At配線
。
出願人代理人 弁理士 鈴 江 武 彦第1図
第2図
第3図
第4図
第5図
第6図1 to 5 are process diagrams for explaining one embodiment of the present invention, and FIG. 6 is a sectional view of a conventional nonvolatile memory. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Memory cell part, 5...
Post-oxidation film, 6... PSG film, 7... Contact hole, 1)... S s 5N4 film, 12... At wiring. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (2)
ルと、このメモリセルを覆う層間絶縁膜と、この絶縁膜
に設けられたコンタクトホールと、このコンタクトホー
ルを通る金属配線層と、この層と前記コンタクトホール
の内壁との間に設けられSiO_2膜より正の可動イオ
ンを通しにくい層とを具備したことを特徴とする不揮発
性半導体メモリ。(1) A nonvolatile semiconductor memory cell formed on a semiconductor substrate, an interlayer insulating film covering this memory cell, a contact hole provided in this insulating film, a metal wiring layer passing through this contact hole, and this layer. A nonvolatile semiconductor memory characterized by comprising a layer provided between the inner wall of the contact hole and a layer through which positive mobile ions are more difficult to pass than the SiO_2 film.
る工程と、前記メモリセルを覆う層間絶縁膜を形成する
工程と、前記層間絶縁膜にコンタクトホールを形成する
工程と、前記コンタクトホールの内壁にSiO_2膜よ
り正の可動イオンを通しにくい層を形成する工程と、前
記コンタクトホールを通る金属配線層を形成する工程と
、前記可動イオンを通しにくい層を形成後、前記金属配
線層を形成する前に700℃以上の高温にする工程とを
具備したことを特徴とする不揮発性半導体メモリの製造
方法。(2) forming a nonvolatile semiconductor memory cell on a semiconductor substrate; forming an interlayer insulating film covering the memory cell; forming a contact hole in the interlayer insulating film; A step of forming a layer through which positive mobile ions are more difficult to pass than the SiO_2 film, a step of forming a metal wiring layer passing through the contact hole, and a step after forming the layer through which mobile ions are more difficult to pass, but before forming the metal wiring layer. 1. A method for manufacturing a nonvolatile semiconductor memory, comprising the steps of: heating the memory to a high temperature of 700° C. or higher.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62047731A JPS63215080A (en) | 1987-03-04 | 1987-03-04 | Nonvolatile semiconductor memory and manufacture thereof |
EP88103309A EP0281140B1 (en) | 1987-03-04 | 1988-03-03 | Semiconductor memory device and method for manufacturing the same |
DE88103309T DE3880860T2 (en) | 1987-03-04 | 1988-03-03 | Semiconductor memory device and method for its production. |
KR1019880002226A KR910008988B1 (en) | 1987-03-04 | 1988-03-04 | Semiconductor device and method for manufacturing the same |
US08/623,882 US5679590A (en) | 1987-03-04 | 1996-03-29 | Method for manufacturing contact hole for a nonvolatile semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62047731A JPS63215080A (en) | 1987-03-04 | 1987-03-04 | Nonvolatile semiconductor memory and manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63215080A true JPS63215080A (en) | 1988-09-07 |
JPH0563029B2 JPH0563029B2 (en) | 1993-09-09 |
Family
ID=12783485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62047731A Granted JPS63215080A (en) | 1987-03-04 | 1987-03-04 | Nonvolatile semiconductor memory and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63215080A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0371626A (en) * | 1989-08-10 | 1991-03-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54139486A (en) * | 1978-04-21 | 1979-10-29 | Hitachi Ltd | Manufacture of semiconductor device |
JPS59144174A (en) * | 1983-02-08 | 1984-08-18 | Nec Corp | Semiconductor device |
-
1987
- 1987-03-04 JP JP62047731A patent/JPS63215080A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54139486A (en) * | 1978-04-21 | 1979-10-29 | Hitachi Ltd | Manufacture of semiconductor device |
JPS59144174A (en) * | 1983-02-08 | 1984-08-18 | Nec Corp | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0371626A (en) * | 1989-08-10 | 1991-03-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0563029B2 (en) | 1993-09-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |