JP2000077544A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element which is provided with a buffer layer of good interface characteristics and film characteristics for preventing diffusion of a metal element from a ferroelectrics film to a silicon substrate, by providing an oxynitride layer as a buffer layer between the ferroelectrics film and the silicon substrate. SOLUTION: An SiON film 3 is formed as a buffer layer on a silicon substrate 1, and a ferroelectric film 4 and a gate insulating film 5 are formed into an island-shape on the SiON film 3. Since the SiON film is tighter in structure than a silicon oxide film, the ability for suppressing the diffusion of a metal element constituting a ferroelectrics is high. By controlling the nitrogen concentration in the film to 10% or below, interface characteristics and in-film fixed charge density which is about the same level as the silicon oxide film are provided. So, by using the SiON film, the metal diffusion from a ferroelectrics is prevented with a film which is thinner than the silicon oxide film while such interface and film characteristics of as almost the same level of the silicon oxide film are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a ferroelectric formed on silicon.

[0002]

2. Description of the Related Art A nonvolatile memory device using a ferroelectric film as a gate insulating film (Metal-Ferroelectric-Semicondu
ctor Field Effect Transistor (MFSFET) is a storage device that is expected to have advantages such as high density and non-destructive readout. In order to realize the MFSFET, it is necessary to form a ferroelectric film having good characteristics on a silicon substrate. However, when a ferroelectric film is formed directly on a silicon substrate, an interface reaction occurs between the silicon substrate and the ferroelectric film, and it is difficult to form a ferroelectric film having good characteristics on the silicon substrate. .

Therefore, attempts have been made to suppress the interfacial reaction by inserting a buffer layer made of an insulator at the interface between the ferroelectric and silicon. Conventionally, there have been reports using a silicon oxide film and a silicon nitride film as a buffer layer. The advantages and problems in each case are described below. (1) When a silicon oxide film is used as a buffer layer This has the advantage that excellent electrical properties of the interface can be utilized. On the other hand, since the silicon oxide film is not structurally dense, the metal element constituting the ferroelectric film on the silicon oxide film diffuses into the silicon oxide film, and furthermore, there is a problem that the metal element reacts with the silicon substrate. is there. When the metal element diffused in the silicon oxide film reaches the silicon substrate, a deep level or the like is formed in a channel portion of the MFSFET, which adversely affects device characteristics.
This diffusion can be prevented to some extent by increasing the thickness of the silicon oxide film. However, while the silicon oxide film has a low dielectric constant, the ferroelectric film generally has a high dielectric constant, and the ratio reaches as high as about 100. From this,
An increase in the thickness of the silicon oxide film undesirably causes an adverse effect of extremely lowering the electric field in the ferroelectric. (2) When Using Silicon Nitride Film as Buffer Layer The silicon nitride film is dense in structure, and is considered to play a role in preventing diffusion of metal elements constituting the ferroelectric film. However, the electrical characteristics of the interface between the silicon nitride film and the silicon substrate are not ideal, and usually include many interface states. Further, it is difficult to obtain a good film of the silicon nitride film itself, and the film contains many electronic trap levels. These interface states and traps in the film are not desirable because they shield the polarization information of the ferroelectric.

[0004]

As described above, even when a silicon oxide film or a silicon nitride film is used as a buffer layer, it is possible to suppress the diffusion of metal elements from the ferroelectric film to the silicon substrate, and to improve the interface characteristics and film characteristics. It has been difficult to overcome all of the suppression of the effect of blocking the polarization information of the ferroelectric due to the poor characteristics.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device having a buffer layer which prevents diffusion of a metal element from a ferroelectric film to a silicon substrate and provides good interface characteristics and film characteristics. An object is to provide an element and a method for manufacturing the element.

[0006]

In order to achieve the above object, the present invention provides a silicon substrate, an SiON film formed on the silicon substrate, and a ferroelectric film formed on the SiON film. And a semiconductor device comprising:

Further, the present invention provides a silicon substrate, a SiN film formed on the silicon substrate, a SiON film formed on the SiN film, and a ferroelectric film formed on the SiON film. There is provided a semiconductor element characterized by comprising:

Further, the present invention provides a semiconductor device wherein the nitrogen concentration in the SiON film is 5% or more and 10% or less. The present invention also provides a step of forming a SiN film by nitriding the surface of a silicon substrate, a step of forming a ferroelectric film on the SiN film, and a step of heat-treating the ferroelectric film and the SiN film. Converting the at least a part of the SiN film into a SiON film by causing the chemical reaction described above. The present invention also provides a method for manufacturing a semiconductor device, wherein the nitriding is performed by ion-implanting N into the surface of a silicon substrate.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is characterized in that an oxynitride (hereinafter referred to as SiON) layer is arranged as a buffer layer between a ferroelectric film and a silicon substrate. Si
Since the ON film is denser than the silicon oxide film,
It has a high ability to suppress the diffusion of the metal element constituting the ferroelectric. By controlling the nitrogen concentration in the SiON film to 10% or less, it is possible to obtain the same interface characteristics and fixed charge density in the film as the silicon oxide film. Therefore, S
By using the iON film, it is possible to prevent metal diffusion from the ferroelectric by using a film thinner than the silicon oxide film while having the same interface characteristics and film characteristics as the silicon oxide film.

Hereinafter, a semiconductor device having a ferroelectric film / SiON / silicon structure and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an MFSFET according to a first embodiment of the present invention. An SiON film 3 is formed on a silicon substrate 1 as a buffer layer.
A ferroelectric film 4 and a gate electrode 5 are formed on the ON film 3 in an island shape. An interlayer insulating film 7 is formed to cover this island. Source / drain regions 6 are formed on both sides of the island of the silicon substrate 1, a part of the interlayer insulator 7 is removed, and the electrodes are taken out to the outside by the wiring electrodes 8.
Makes up ET. 2 is an element isolation region.

Next, a method of manufacturing the MFSFET will be described with reference to the drawings. First, as shown in FIG. 2, an element isolation region 2 is formed in a silicon substrate 1. In this embodiment, the trench 2 is formed as an element isolation region.

Next, as shown in FIG. 3, a heat treatment in an oxynitriding atmosphere is performed on the surface of the silicon substrate 1 from which the elements have been separated, and the nitrogen concentration in the film is 5% or more and 10% or less.
An iON film 3 is formed. The thickness of the SiON film 3 is preferably 5 nm or more. The deposition method of the SiON film 3 is CVD (Ch
An emical vapor deposition method, a process such as a heat treatment in a nitriding atmosphere of a silicon oxide film, or the like may be used.

Next, as shown in FIG. 3, on this substrate,
For example, by a sol-gel method, a ferroelectric film 4 such as SrBi ₂
Ta ₂ O ₉ (hereinafter SBT) is deposited. As the ferroelectric film 4
Any material such as Pb (Zr, Ti) O ₃ (PZT) and Bi ₄ Ti ₃ O ₁₂ (BiTO) may be used, and the film formation method may be a method other than the sol-gel method.

The conditions for forming the ferroelectric film 4 by the sol-gel method are as follows.
m, and a rotation time of 20 seconds. After spin coating, dry the sample at 200 ° C for 5 minutes to evaporate the solvent in the solution. After repeating the spin coating and drying processes three times, heat treatment is performed at 800 ° C. for 30 minutes in an oxygen atmosphere at atmospheric pressure to crystallize SBT. The thickness of the SBT film 4 thus formed is about 300 nm.

Next, as shown in FIG. 3, a metal serving as the gate electrode 5, for example, a Pt electrode film 5 is deposited on the sample by about 50 nm by an electron beam evaporation method. The material of the gate electrode 5 is not limited to Pt, but may be Ir, Ru, Au, IrO2, RuO2.
For example, any conductive material having oxidation resistance may be used. In this embodiment, after Pt deposition, the substrate is heat-treated at 800 ° C. for 30 minutes in an oxygen atmosphere in order to improve the crystallinity of SBT.

Next, as shown in FIG. 4, in order to form the gate electrode 5, a resist pattern of the gate electrode 5 is formed by, for example, photolithography. After that, the Pt gate electrode 5, the SBT film 4, and the SiON film 3 are etched.
In this embodiment, the Pt gate electrode 5 and the SBT film 4 were dry-etched by Ar ion milling, and the remaining SiON film 3 was processed by reactive ion etching.

A resist mask for ion implantation was formed on the sample thus obtained, impurity ions were implanted by ion implantation, and heat treatment was performed to form source / drain regions 6. After that, an MFSFET shown in FIG. 1 can be obtained by depositing an interlayer insulating film 7 by a conventional technique, opening a contact hole, and depositing, for example, an Al electrode 8 as a contact wiring.

According to this embodiment, since the SiON buffer layer 3 is formed between the ferroelectric film 4 and the silicon substrate 1, the metal element forming the ferroelectric
An MFSFET that prevents diffusion into the interior and has good interface characteristics and film characteristics can be realized.

FIG. 5 is a sectional view of an MFSFET according to a second embodiment of the present invention. An SiON film 3 is formed on a silicon substrate 1 as a buffer layer.
A ferroelectric film 4 and a gate electrode 5 are formed on the ON film 3 in an island shape. In this MFSFET, as an element isolation region 2,
The elements are separated by LOCOS 2. Source / drain regions 6 are formed on both sides of the island of the silicon substrate 1, and the electrodes are taken out by wiring electrodes 8 to form an MFSFET.

Hereinafter, a method of manufacturing the MFSFET will be described.
This will be described with reference to the drawings. In this embodiment, the SiON buffer layer 3 between the ferroelectric film 4 and the silicon substrate 1 is formed, the SiN film 9 is formed on the silicon substrate 1, and then the ferroelectric film 4 is formed. It is characterized in that it is formed by oxidizing the SiN film 9 by oxygen therein.

First, as shown in FIG. 6, a resist mask for ion implantation is formed on a silicon substrate 1 having an element isolation region, impurity ions are implanted, and heat treatment is performed to form source / drain regions 6. Form. Here, the element isolation region 2 has a LOCOS structure 2 as an example.

Next, as shown in FIG. 7, on this substrate,
For example, a silicon nitride film 9 is formed by a CVD method. The thickness of the silicon nitride film 9 is preferably 5 nm or more. Regarding the method of depositing the silicon nitride film 9, the silicon substrate 1
Or a method in which the silicon substrate 1 is thermally nitrided, and a method in which the silicon nitride film is volumetrically formed by CVD.

Next, as shown in FIG. 8, on this substrate,
A ferroelectric film 4, for example, an SBT film 4 is formed by a sol-gel method or the like. Thereafter, the silicon nitride film 9 was oxidized by the ferroelectric film 4 and converted into the SiON film 3 by subjecting the substrate to a heat treatment in an oxygen atmosphere at 800 ° C. The oxygen heat treatment for converting the silicon nitride film 9 into the SiON film 3 may be the oxygen heat treatment for simultaneously crystallizing the ferroelectric film 4.

Also, the structure of the ferroelectric film / SiON film / silicon nitride film / silicon substrate may not be completely oxidized but remain. Thereafter, a metal material to be the gate electrode 5, for example, a Pt electrode 5 is deposited. The Pt film 5, the SBT film 4, and the SiON buffer layer 3 are etched by a conventional technique such as dry etching using a resist mask for a contact hole, then a gate mask pattern is formed, and the Pt is etched to form a gate electrode 5. . Then, as a contact / wiring, for example, an Al electrode 8
FIG. 5 is obtained by depositing
The MFSFET of the second embodiment shown in FIG.

According to the present embodiment, the SiON film 3 is formed by oxidizing the silicon nitride film 9. This S
The iON film 3 prevents the metal element constituting the ferroelectric film 4 from diffusing into the silicon substrate 1 and provides good interface characteristics.
An MFSFET having film characteristics can be realized.

(Embodiment 3) FIG. 9 is a sectional view of an MFSFET according to a third embodiment of the present invention. An SiON film 3 is formed as a buffer layer 3 on a silicon substrate 1.
On the iON film 3, a ferroelectric film 4 and a gate electrode 5 are formed in an island shape. In this MFSFET, elements are separated by LOCOS2. Source / drain regions 6 are formed on both sides of the island of the silicon substrate 1, and the electrodes are taken out by wiring electrodes 8 to form an MFSFET. Reference numeral 7 denotes an interlayer insulating film.

In the following, a method of manufacturing this MFSFET will be described.
This will be described with reference to the drawings. In this embodiment, the silicon substrate 1 controlled to be rich in nitrogen is
An N film 3 was formed.

First, as shown in FIG. 10, nitrogen ions are implanted on a silicon substrate 1 having an element isolation region 2 under the conditions of an acceleration energy of 20 keV and an implantation amount of 5 × 10 ¹⁴ cm ⁻² , for example. The surface modification layer 10 is formed. Nitrogen ion implantation may be performed by directly implanting ions into the silicon substrate 1 or by forming a passivation film such as a silicon oxide film on the surface of the silicon substrate 1 and implanting nitrogen ions through the passivation film. Further, the silicon substrate 1 may be exposed to nitrogen plasma for forming a nitrogen-rich silicon surface layer. At this time, at least the surface of the silicon substrate 1 may be modified to be nitrogen-rich. The thickness from the surface of the nitrogen-modified silicon is preferably 5 nm or more.

Next, as shown in FIG. 11, a ferroelectric film 4 such as SB is formed on this substrate by a sol-gel method or the like.
A T film 4 is formed. Thereafter, the N implanted layer 10 is oxidized by the ferroelectric film 4 and converted into the SiON film 3 by heat treatment in an oxygen atmosphere at 800 ° C., whereby the ferroelectric film / Si
An ON film / silicon structure is formed. Further, the method of forming the SiON film 3 on the surface of the nitrogen-rich silicon substrate 1 may be performed by oxygen heat treatment for crystallizing the ferroelectric film.

Thereafter, a metal material to be the gate electrode 5, for example, a Pt gate electrode 5 is deposited. Next, as shown in FIG. 12, a resist pattern for the gate electrode is formed. Thereafter, the Pt gate electrode 5, the SBT film 4, and the SiON film 3 are removed by, for example, dry etching. A resist mask for ion implantation is formed on the substrate thus obtained, impurity ions are implanted by an ion implantation method, and heat treatment is performed to form source / drain regions 6.

Thereafter, the interlayer insulating film 7 is formed by a conventional technique.
Is deposited, a contact hole is opened, and a contact wiring 8 is formed.
For example, by depositing an Al electrode 8 and processing Al, the MFSFET of this embodiment shown in FIG. 9 can be obtained.

According to the present embodiment, a ferroelectric film / SiON film / silicon structure could be obtained by converting the nitrogen-rich silicon surface into the SiON film 3. Also in the present embodiment, the metal element forming the ferroelectric film 5 is prevented from diffusing into the silicon substrate 1, and an MFSFET having good interface characteristics and film characteristics can be realized.

[0034]

As described in detail above, the ferroelectric film / SiON film / silicon structure of the present invention suppresses the diffusion of the metal elements constituting the ferroelectric film into the silicon substrate and has good interface characteristics. In addition, the effect of not deteriorating the ferroelectric characteristics due to the existence of the interface SiON film itself can be expected, and the performance of the nonvolatile memory using the ferroelectric film can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of an MFSFET according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the MFSFET according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing process of the MFSFET according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of the MFSFET according to the first embodiment of the present invention.

FIG. 5 is a sectional view of an MFSFET according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the MFSFET according to the second embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of the MFSFET according to the second embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of the MFSFET according to the second embodiment of the present invention.

FIG. 9 is a sectional view of an MFSFET according to a third embodiment of the present invention.

FIG. 10 is a sectional view showing the manufacturing process of the MFSFET according to the third embodiment of the present invention.

FIG. 11 is a sectional view showing a manufacturing process of the MFSFET according to the third embodiment of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the MFSFET according to the third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation region 3 SiON buffer film 4 ferroelectric film 5 gate electrode 6 source / drain region 7 interlayer insulating film 8 electrode 9 SiN film 10 N implant layer

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Go Yamaguchi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5F001 AA17 AD12 AD60 AD62 AG10 AG12 AG21 AG23 5F083 FR06 JA05 JA14 JA15 JA17 JA19 JA38 JA43 NA01 NA02 PR03 PR15 PR21 PR33 PR36

Claims (5)

[Claims] 1. A semiconductor device comprising: a silicon substrate; a SiON film formed on the silicon substrate; and a ferroelectric film formed on the SiON film. 2. A semiconductor device comprising: a silicon substrate; a SiN film formed on the silicon substrate; a SiON film formed on the SiN film; and a ferroelectric film formed on the SiON film. Characteristic semiconductor element. 3. The nitrogen concentration in said SiON film is not less than 5% and not more than 1.
3. The semiconductor device according to claim 1, wherein the content is 0% or less. 4. The method according to claim 1, wherein the surface of the silicon substrate is nitrided.
Forming a SiN film; forming a ferroelectric film on the SiN film; and causing a chemical reaction between the ferroelectric film and the SiN film by heat treatment, thereby forming at least a portion of the SiN film. Converting a silicon nitride film into an SiON film. 5. The method according to claim 4, wherein the nitriding is performed by ion-implanting N into the surface of the silicon substrate.