JPS63205975A - Manufacture of josephson junction device - Google Patents
Manufacture of josephson junction deviceInfo
- Publication number
- JPS63205975A JPS63205975A JP62037801A JP3780187A JPS63205975A JP S63205975 A JPS63205975 A JP S63205975A JP 62037801 A JP62037801 A JP 62037801A JP 3780187 A JP3780187 A JP 3780187A JP S63205975 A JPS63205975 A JP S63205975A
- Authority
- JP
- Japan
- Prior art keywords
- josephson junction
- lower electrode
- film
- unevenness
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 7
- 239000002887 superconductor Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 35
- 238000004544 sputter deposition Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000010955 niobium Substances 0.000 description 22
- 229910052758 niobium Inorganic materials 0.000 description 15
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910017107 AlOx Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は超伝導集積回路等に用いるジョセフソン接合素
子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a Josephson junction element used in superconducting integrated circuits and the like.
（従来の技術）
ニオブ（Ｎｂ）は機械的に強く、耐熱性にもすぐれた超
伝導材料であるため、超伝導集積回路は通常ニオブを用
いて形成される。第４図はニオブを電極材料として用い
た超伝導集積回路の断面図である。第４図におｐｓて、
グランドプレーン３２、コンタクトホール３３、下部配
線３５、下部電極３６、上部電極３８、上部配線３９は
、すべてニオブをスパッタで成膜し、フッ素系ガスを用
いた反応性イオンエツチングで加工することによって得
られる。抵抗３４はモリブデンを材料に用い、スパッタ
で成膜し、フッ素系ガスによる反応性イオンエツチング
で加工することによって得られる。また第４図に示す超
伝導集積回路においては、層間絶縁膜である二酸化シリ
コンを用いて各層表面の平坦化を行っている。(Prior Art) Niobium (Nb) is a superconducting material that is mechanically strong and has excellent heat resistance, so superconducting integrated circuits are usually formed using niobium. FIG. 4 is a cross-sectional view of a superconducting integrated circuit using niobium as an electrode material. In Figure 4 ps,
The ground plane 32, contact hole 33, lower wiring 35, lower electrode 36, upper electrode 38, and upper wiring 39 are all obtained by forming a niobium film by sputtering and processing it by reactive ion etching using fluorine gas. It will be done. The resistor 34 is obtained by using molybdenum as a material, forming a film by sputtering, and processing it by reactive ion etching using fluorine gas. Furthermore, in the superconducting integrated circuit shown in FIG. 4, the surface of each layer is planarized using silicon dioxide, which is an interlayer insulating film.
下部電極３６上に、アルミニウムを成膜し、その表面を
酸化することによってアルミニウム酸化物（ＡｌｏＸ）
を形成し、このＡｌＯｘをトンネル障壁層３７とするＮ
ｂ／ＡｌＯｘ／Ｎｂ接合は、ニオブの酸化膜をトンネル
障壁層として用いた接合に比べて、接合特性が格段に優
れている。このため第４図に示す超伝導集積回路に用い
るジョセフソン接合としては、前述の下部電極３６．上
部電極３８にニオブを用い、トンネル障壁層３７にアル
ミニウム酸化膜を用いたＮｂ／ＡｌＯｘ／Ｎｂ接合が用
いられる。Aluminum oxide (AloX) is formed by forming an aluminum film on the lower electrode 36 and oxidizing its surface.
is formed, and this AlOx is used as the tunnel barrier layer 37.
The b/AlOx/Nb junction has much better junction characteristics than a junction using a niobium oxide film as a tunnel barrier layer. Therefore, the Josephson junction used in the superconducting integrated circuit shown in FIG. A Nb/AlOx/Nb junction is used in which niobium is used for the upper electrode 38 and an aluminum oxide film is used for the tunnel barrier layer 37.
（発明が解決しようとする問題点）
第４図に示すように超伝導集積回路においては、ジョセ
フソン接合より下層に、グランドブレーン３２や層間絶
縁膜、下部配線３５等のいくつかの層が形成されている
。これらの各層やコンタクトホール３３、抵抗３４の形
成のために、各層表面は、反応性イオンエツチングやウ
ェットエツチングにさらされ、表面に凹凸が生じる。ま
たスパッタによる成膜時にも多少の凹凸は生じる。この
ためジョセフソン接合の下部電極３６成膜前の下部配線
３５表面には、数＋ｎｍから数百ｎｍにおよぶ凹凸がで
きる。(Problems to be Solved by the Invention) As shown in FIG. 4, in a superconducting integrated circuit, several layers such as a ground brain 32, an interlayer insulating film, and a lower wiring 35 are formed below the Josephson junction. has been done. In order to form each of these layers, the contact hole 33, and the resistor 34, the surface of each layer is exposed to reactive ion etching or wet etching, resulting in unevenness on the surface. Also, some unevenness occurs during film formation by sputtering. For this reason, the surface of the lower wiring 35 before the lower electrode 36 of the Josephson junction is formed has irregularities ranging from several + nanometers to several hundred nanometers.
そのため下部電極３６を通常のスパッタ法で下部配線３
５上に成膜すると、同程度の凹凸がトンネル障壁層３７
と接する下部電極３６表面に生じていた。Therefore, the lower electrode 36 is formed on the lower wiring 3 by a normal sputtering method.
When a film is formed on the tunnel barrier layer 37, the same degree of unevenness is formed on the tunnel barrier layer 37.
This occurred on the surface of the lower electrode 36 that was in contact with the surface of the lower electrode 36.
一方、従来の技術で述べたＮｂ／ＡｌＯｘ／Ｎｂ接合に
おけるアルミニウム膜厚の最適値は、電子通信学会技術
報告、ＣＭＰ８５−１．１９８５年にあたるように、数
ｎｍと非常に薄い。このため下部電極３６表面に凹凸が
あると、アルミニウムによるニオブのカバレージが悪く
なり、リーク電流が発生して接合特性が劣化するという
問題があった。On the other hand, the optimal value of the aluminum film thickness in the Nb/AlOx/Nb junction described in the prior art is very thin, several nanometers, as described in the Technical Report of Institute of Electronics and Communication Engineers, CMP85-1.1985. Therefore, if the surface of the lower electrode 36 is uneven, there is a problem in that coverage of niobium by aluminum is poor, leakage current is generated, and bonding characteristics are deteriorated.
本発明は、上記従来の技術の欠点を克服し、下地に凹凸
がある場合でも接合特性の劣化を生じないジョセフソン
接合素子の製造方法を提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the above-mentioned conventional techniques and to provide a method for manufacturing a Josephson junction element that does not cause deterioration of the junction characteristics even when the underlying surface is uneven.
（問題点を解決するための手段〕
本発明によれば、基板上に形成される超伝導装置に用い
られる超伝導体からなる下部電極と上部電極がトンネル
障壁層を介して結合したトンネル型ジョセフソン接合素
子の製造方法において、前記ジョセフソン接合素子と接
する下地の凹凸を緩和する平坦化を施す工程を含むこと
を特徴とするジョセフソン接合素子の製造方法が得られ
る。(Means for Solving the Problems) According to the present invention, there is provided a tunnel type Joseph in which a lower electrode and an upper electrode made of a superconductor are coupled via a tunnel barrier layer to be used in a superconducting device formed on a substrate. A method for manufacturing a Josephson junction element is obtained, which includes a step of flattening a base in contact with the Josephson junction element to reduce unevenness.
（作用）
本発明の製造方法においては、まず下地表面の平坦化を
行ってから、その上にジョセフソン接合素子の下部電極
を成膜している。そのため、下部電極表面がより平坦に
なり、前述のアルミニウム等のトンネル障壁層材料とな
る金属による下部電極表面のカバレージが向上する。こ
のため、下地の凹凸の影響を受けない高品質のジョセフ
ソン接合素子が得られる。(Function) In the manufacturing method of the present invention, the underlying surface is first flattened, and then the lower electrode of the Josephson junction element is formed thereon. Therefore, the surface of the lower electrode becomes flatter, and the coverage of the surface of the lower electrode by the aforementioned metal, such as aluminum, which is the material of the tunnel barrier layer is improved. Therefore, a high quality Josephson junction element that is not affected by the unevenness of the underlying material can be obtained.
（実施例１）
第１図は本発明の第１の実施例を説明するための概略断
面図であり、超伝導集積回路の下部配線より上層を示し
ている。(Example 1) FIG. 1 is a schematic cross-sectional view for explaining the first example of the present invention, showing the upper layer from the lower wiring of a superconducting integrated circuit.
表面に３０ｎｍ程度の凹凸のあるニオブからなる下部配
線１１上に、アルゴンガス圧１．９Ｐａ、基板バイアス
−２００ｖのバイアススパッタでニオブを厚さ５０ｎｍ
成膜し、平坦化層１２とする。基板に負のバイアスをか
けるバイアススパッタ法では、ジャーナル・オブ・バキ
ウムサイエンステクノロジー（Ｊｏｕｒｎａｌｏｆ Ｖ
ａｃｕｕｍ ５ｃｉｅｎｃｅ Ｔｅｃｈｎｏｌｏｇｙ）
第１５巻、第１１０５頁、１９７８年にあるように突出
した部分をエツチングしなから成膜が行われるため下部
配線１１表面の凹凸は緩和され、平坦化層１２表面には
、凹凸はほとんど残らない。この表面の平坦な平坦化層
１２上に、アルゴンガス圧１．９Ｐａの条件で基板にバ
イアスをがけない通常のスパッタ法を用いてニオブを２
７０ｎｍ成膜し下部電極１３とする。下部電極１３上に
アルミニウムを３ｎｍ成膜し、その表面を４０Ｐａ、１
０分間の熱酸化法によって酸化することによってアルミ
ニウム酸化膜からなるトンネル障壁層１４を形成する。Niobium is deposited to a thickness of 50 nm on the lower wiring 11 made of niobium, which has an uneven surface of about 30 nm, by bias sputtering at an argon gas pressure of 1.9 Pa and a substrate bias of -200 V.
A film is formed to form a planarization layer 12. The bias sputtering method, which applies a negative bias to the substrate, is described in the Journal of Bachium Science and Technology (Journalof V
acum 5science Technology)
As described in Vol. 15, p. 1105, 1978, since the film is formed without etching the protruding parts, the unevenness on the surface of the lower wiring 11 is alleviated, and almost no unevenness remains on the surface of the planarization layer 12. do not have. Niobium was deposited on the planarization layer 12 with a flat surface using a normal sputtering method under the condition of an argon gas pressure of 1.9 Pa without applying a bias to the substrate.
A 70 nm film is formed to form the lower electrode 13. A 3 nm thick aluminum film was formed on the lower electrode 13, and the surface was heated to 40 Pa and 1
A tunnel barrier layer 14 made of an aluminum oxide film is formed by oxidizing by a thermal oxidation method for 0 minutes.
次に上部電極１５としてニオブをアルゴンガス圧１．９
Ｐａの通常のスパッタ法で２００ｎｍ成膜する。以上述
べた平坦化層１２から上部電極１５までの接合構成層を
四フッ化炭素（ＣＦ４）ガスを用いた反応性イオンエツ
チングで加工しジョセフソン接合素子を形成する。接合
の周囲を二酸化シリコン（Ｓｉ０２）工し、上部配線１
７とし、第１図に示す超伝導集積回路とする。Next, niobium was used as the upper electrode 15 at an argon gas pressure of 1.9
A film of 200 nm is formed using a normal sputtering method using Pa. The junction constituent layers from the planarization layer 12 to the upper electrode 15 described above are processed by reactive ion etching using carbon tetrafluoride (CF4) gas to form a Josephson junction element. Silicon dioxide (Si02) is applied around the junction, and the upper wiring 1
7, and the superconducting integrated circuit shown in FIG.
以上述べた本実施例においては、下部電極３６表面の凹
凸はバイアススパッタ法による平坦化層１２によって緩
和されるため、トンネル障壁層１４部分の３ｎｍのアル
ミニウムによるニオブのカバレージに及ぼす影響は小さ
くなる。しかしスインソリッドフィルムス（Ｔｈｉｎ
５ｏｌｉｄ Ｆｉｌｍｓ）第６４巻、第１０３頁、１９
７９年にあるように前記スパッタ条件で成膜した平坦化
層１２はアルゴンを約１％含み、超伝導臨界温度が８．
８にとバルクの値９．２により低い超伝導特性の劣った
ニオブ膜となっている。このため、平坦化層１２をジョ
セフソン接合素子の下部電極として用いその上にトンネ
ル障壁層を形成すると、エネルギーキャップが小さい等
、特性の劣ったジョセフソン接合素子となる。そこで本
実施例においては、トンネル障壁層１４は、超伝導臨界
温度が９゜２にの優れた超伝導特性を有するニオブ膜か
らなる下部電極１３上に形成している。In this embodiment described above, the unevenness on the surface of the lower electrode 36 is alleviated by the planarizing layer 12 formed by bias sputtering, so that the influence of the 3 nm aluminum of the tunnel barrier layer 14 on the coverage of niobium is reduced. However, Thin Solid Films
5solid Films) Volume 64, Page 103, 19
The planarization layer 12 formed under the sputtering conditions described in 1979 contains about 1% argon and has a superconducting critical temperature of 8.5%.
8 and the bulk value of 9.2, it is a niobium film with poor superconducting properties. Therefore, if the planarization layer 12 is used as the lower electrode of a Josephson junction element and a tunnel barrier layer is formed thereon, the Josephson junction element will have poor characteristics such as a small energy cap. Therefore, in this embodiment, the tunnel barrier layer 14 is formed on the lower electrode 13 made of a niobium film having excellent superconducting properties with a superconducting critical temperature of 9.degree.
以上説明したように、本実施例による製造方法を用いれ
ば、下部電極の超伝導臨界温度等の超伝導特性を損うこ
となく、ジョセフソン接合素子の下地の凹凸の緩和が行
われるため、下地に凹凸がある場合でもリーク電流のな
い高品質のジョセフソン素子を形成できる。また、本実
施例で述べた平坦化層１２は、下部電極１３と同一の真
空室中で成膜でき、加工も下部電極１３と同じエツチン
グ工程で行えるため、製造プロセスが煩雑になることも
ない。As explained above, if the manufacturing method according to this embodiment is used, the unevenness of the base of the Josephson junction element can be alleviated without impairing the superconducting properties such as the superconducting critical temperature of the lower electrode. A high-quality Josephson device with no leakage current can be formed even when the surface has irregularities. Furthermore, the flattening layer 12 described in this embodiment can be formed in the same vacuum chamber as the lower electrode 13, and can be processed in the same etching process as the lower electrode 13, so the manufacturing process does not become complicated. .
（実施例２）
第２図（ａ）〜（ｄ）は、本発明の第２の実施例を説明
するための概略断面図である。以下第２図を用いて本発
明の第２の実施例の説明を行う。(Example 2) FIGS. 2(a) to 2(d) are schematic sectional views for explaining a second example of the present invention. A second embodiment of the present invention will be described below with reference to FIG.
第２図（ａ）に示す下部配線２１表面には、そこまでの
製造プロセスによって８０ｎｍの凹凸が生じている。The surface of the lower wiring 21 shown in FIG. 2(a) has an unevenness of 80 nm due to the manufacturing process up to that point.
この下部配線２１上に、フォトレジストＡＺ−１３５０
Ｊ（商品名）を塗布し、２００’Ｃ１６０分間のベーキ
ングを行い、７オトレジストをリフローさせ、第２図（
ｂ）に示す表面の平坦な平坦化膜２２を形成する。On this lower wiring 21, a photoresist AZ-1350 is applied.
J (product name) was applied, baked for 160 minutes at 200'C, and reflowed with 7-otoresist, as shown in Figure 2 (
A planarizing film 22 having a flat surface as shown in b) is formed.
第３図は、石英基板を用いた場合の平行平板型反応性イ
オンエツチング装置における四フッ化炭素（ＣＦ４）ガ
ス圧力とニオブ（Ｎｂ）およびフォトレジスト（ＡＺ１
３５０Ｊ）のエツチングレートとの関係を示したもので
ある。第３図からＣＦ４圧力５．ＯＰａの条件でエッチ
下部配線２１上に平坦化膜２２を形成した膜に対して、
ＣＦ４圧力５．ＯＰａの条件で２分４０秒間のエツチン
グを行うと平坦化膜２２と下部配線２１と合せて２００
ｎｍエツチングされる。しかもこのエツチング条件では
、平坦化膜２２と下部配線２１は同じエツチングレート
でエツチングされるため表面は平坦に保たれたままであ
る。以上述べたエッチバックのプロセスにより下部配線
２１表面は第２図（Ｃ）に示すように平坦となる。Figure 3 shows the relationship between carbon tetrafluoride (CF4) gas pressure and niobium (Nb) and photoresist (AZ1) in a parallel plate reactive ion etching apparatus using a quartz substrate.
350J) and the etching rate. From Figure 3, CF4 pressure 5. For the film in which the planarization film 22 is formed on the etched lower wiring 21 under OPa conditions,
CF4 pressure5. When etching is performed for 2 minutes and 40 seconds under OPa conditions, a total of 200 mm
nm etched. Moreover, under these etching conditions, the flattening film 22 and the lower wiring 21 are etched at the same etching rate, so the surfaces remain flat. Through the etch-back process described above, the surface of the lower wiring 21 becomes flat as shown in FIG. 2(C).
以下、第１の実施例と同じプロセスによって第２図（ｄ
）に示すジョセフソン接合素子を形成する。Hereinafter, the same process as in the first embodiment is performed as shown in FIG. 2 (d).
) is formed.
本実施例に示したエッチバック法を用いた平坦化方法を
用いればジョセフソン接合素子の下地表面の凹凸が大き
い場合でも、下地表面を平坦にすることができ、リーク
電流のない高品質のジョセフソン接合素子が得られる。If the planarization method using the etch-back method shown in this example is used, even if the underlying surface of the Josephson junction element has large irregularities, the underlying surface can be made flat, and a high-quality Josephson junction device with no leakage current can be obtained. A Son junction device is obtained.
（発明の効果）
以上説明したように本発明によるジョセフソン接合素子
の製造方法は、超伝導集積回路等の製造プロセスにおい
て、ジョセフソン接合素子が形成される下地に凹凸があ
る場合でも、ジョセフソン接合素子の下部電極の超伝導
特性を損なうことなしに前記下地の凹凸を緩和できるた
め、前記下地の超伝導集積回路の断面の一部を示した図
。第２図は本発明の第２の実施例を説明するための概略
断面図。第３図は、平行平板型反応性イオンエツチング
装置におけるＣＦ４圧力とニオブおよびフォトレジス）
（ＡＺ１３５０Ｊ）のエツチングレートの関係を示し
た特性図。第４図は、従来の技術を説明するための超伝
導集積回路の断面を示した図。(Effects of the Invention) As explained above, the method for manufacturing a Josephson junction element according to the present invention allows Josephson FIG. 3 is a diagram illustrating a part of a cross section of a superconducting integrated circuit on the base, since the unevenness of the base can be alleviated without impairing the superconducting properties of the lower electrode of the bonding element. FIG. 2 is a schematic sectional view for explaining a second embodiment of the present invention. Figure 3 shows CF4 pressure and niobium and photoresist in a parallel plate type reactive ion etching apparatus)
(AZ1350J) Characteristic diagram showing the relationship between etching rates. FIG. 4 is a diagram showing a cross section of a superconducting integrated circuit for explaining the conventional technology.
図において
１１・・・下部配線、１２・・・平坦化層、１３・・・
下部電極、１４・・・トンネル障壁層、 １５・・・
上部電極、１６・・・層間絶縁層、 １７・・・
上部配線、２１・・・下部配線、２２・・・平坦化膜、
２３・・・下部電極、２４・・件ンネル障壁層、 ２
５・・・上部電極、。In the figure, 11... lower wiring, 12... flattening layer, 13...
Lower electrode, 14... Tunnel barrier layer, 15...
Upper electrode, 16... Interlayer insulating layer, 17...
Upper wiring, 21... Lower wiring, 22... Flattening film,
23... Lower electrode, 24... Channel barrier layer, 2
5... Upper electrode.
２６・・・層間絶縁層、 ２７・・・上部配線、３１・
・・基板、３２・・・グランドプレーン、３３・・・コ
ンタクトホール、３４・・・抵抗、 ３５・・・下部配
線、 ３６・・・下部電極、３７・・件ンネル障壁層、
３８・・・上部電極、３９・・・上部配線。26... Interlayer insulating layer, 27... Upper wiring, 31...
... Substrate, 32... Ground plane, 33... Contact hole, 34... Resistor, 35... Lower wiring, 36... Lower electrode, 37... Channel barrier layer,
38... Upper electrode, 39... Upper wiring.
Claims (1)
らなる下部電極と上部電極がトンネル障壁層を介して結
合したトンネル型ジョセフソン接合素子の製造方法にお
いて、前記ジョセフソン接合素子と接する下地の凹凸を
緩和する平坦化を施す工程を含むことを特徴とするジョ
セフソン接合素子の製造方法。In a method for manufacturing a tunnel type Josephson junction element in which a lower electrode and an upper electrode made of a superconductor are bonded via a tunnel barrier layer, the lower electrode and the upper electrode made of a superconductor used in a superconducting device formed on a substrate include a base in contact with the Josephson junction element. 1. A method for manufacturing a Josephson junction element, comprising a step of flattening the surface to reduce unevenness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62037801A JPS63205975A (en) | 1987-02-23 | 1987-02-23 | Manufacture of josephson junction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62037801A JPS63205975A (en) | 1987-02-23 | 1987-02-23 | Manufacture of josephson junction device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63205975A true JPS63205975A (en) | 1988-08-25 |
| JPH0556030B2 JPH0556030B2 (en) | 1993-08-18 |
Family
ID=12507611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62037801A Granted JPS63205975A (en) | 1987-02-23 | 1987-02-23 | Manufacture of josephson junction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205975A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018065833A1 (en) * | 2016-10-04 | 2018-04-12 | International Business Machines Corporation | Superconducting electronic integrated circuit |
| WO2018089061A3 (en) * | 2016-08-23 | 2018-07-05 | Northrop Grumman Systems Corporation | Josephson junction superconductor device interconnect |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58145177A (en) * | 1982-02-23 | 1983-08-29 | Nec Corp | Manufacture of josephson junction element |
| JPS6215868A (en) * | 1985-07-13 | 1987-01-24 | Agency Of Ind Science & Technol | Manufacture of contact for integrated circuit |
-
1987
- 1987-02-23 JP JP62037801A patent/JPS63205975A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58145177A (en) * | 1982-02-23 | 1983-08-29 | Nec Corp | Manufacture of josephson junction element |
| JPS6215868A (en) * | 1985-07-13 | 1987-01-24 | Agency Of Ind Science & Technol | Manufacture of contact for integrated circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018089061A3 (en) * | 2016-08-23 | 2018-07-05 | Northrop Grumman Systems Corporation | Josephson junction superconductor device interconnect |
| US10158062B2 (en) | 2016-08-23 | 2018-12-18 | Northrop Grumman Systems Corporation | Superconductor device interconnect |
| JP2019528577A (en) * | 2016-08-23 | 2019-10-10 | ノースロップ グラマン システムズ コーポレイションＮｏｒｔｈｒｏｐ Ｇｒｕｍｍａｎ Ｓｙｓｔｅｍｓ Ｃｏｒｐｏｒａｔｉｏｎ | Interconnection of superconducting devices |
| WO2018065833A1 (en) * | 2016-10-04 | 2018-04-12 | International Business Machines Corporation | Superconducting electronic integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0556030B2 (en) | 1993-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5393709A (en) | Method of making stress released VLSI structure by the formation of porous intermetal layer | |
| JPS63205975A (en) | Manufacture of josephson junction device | |
| US4764483A (en) | Method for burying a step in a semiconductor substrate | |
| JPS6281075A (en) | Manufacture of josephson integrated circuit | |
| KR950006343B1 (en) | Fabricating method of semiconductor device | |
| JP3130726B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH01212439A (en) | Processing of interlayer film | |
| JPH04139828A (en) | Manufacture of semiconductor device | |
| JPS6347947A (en) | Manufacture of semiconductor device | |
| JPH05211355A (en) | Manufacture of josephson integrated circuit | |
| JPH0691051B2 (en) | Method for manufacturing semiconductor device | |
| JP3518083B2 (en) | Substrate manufacturing method | |
| JPS60115234A (en) | Preparation of semiconductor device | |
| JP2937675B2 (en) | Method for manufacturing semiconductor device | |
| JPS58125880A (en) | Josephson junction element | |
| JP2991388B2 (en) | Method for manufacturing semiconductor device | |
| JPH07321202A (en) | Forming method for multilayer interconnection | |
| JPS61208879A (en) | Manufacture of josephson integrated circuit | |
| JPS63192283A (en) | Formation of superconducting line | |
| JPS6322067B2 (en) | ||
| JPS6362255A (en) | Method for flattening semiconductor device | |
| JPS5826659B2 (en) | Electrode formation method for semiconductor devices | |
| JPH058596B2 (en) | ||
| JPS60233840A (en) | Coating method for stepwise difference | |
| JPS62224937A (en) | Recession filling process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |