JPS6215868A - Manufacture of contact for integrated circuit - Google Patents

Abstract

PURPOSE:To enable the formation of a superconducting contact of a complete planar structure by disposing an insulating layer over a resist pattern and a first superconducting wiring layer, removing the resist pattern and the insulating layer thereon, and forming on the surface thereof a second superconducting wiring layer. CONSTITUTION:A first superconducting wiring layer 2 is disposed on a substrate 1, a resist pattern 3 for forming a superconducting contact is formed on the superconducting wiring layer 2, and etching is performed through the resist pattern to form a contact region 2A. Then, after disposing an insulating layer 4 over the resist pattern 3 and the first superconducting wiring layer 2, the resist pattern 3 and the insulating layer 4 on the resist pattern 3 are removed, and a second superconducting wiring layer 7 is formed on the surfaces of the insulating layer 4 and the exposed first superconducting wiring layer 2A. Further, for instance, a process is added during these steps, where a planarized layer 5 such as spin-on glass or organic silicon is deposited, and the planarized layer 5 is etched away to the surface of the insulating layer 4 except for the portion 5A of the planarized layer 5 which penetrated into the groove 6 formed between the insulating layer 4 and the contact region 2A.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming contacts with a completely planar structure in integrated circuits, such as superconducting integrated circuits.

U. Prior Art J In recent years, logic circuits using superconducting development have attracted attention because they have low power consumption, are suitable for high-density integration, and are expected to perform extremely high-speed logic operations. In particular, Josephson junctions as logic elements that utilize superconductivity are being actively researched with the aim of applying them to ultra-high-speed computers.

In conventional superconducting integrated circuits, superconducting contacts between superconducting wiring layers, that is, contacts for connecting two wiring layers while maintaining a superconducting state, are made using an insulating layer extending beyond the wiring layers. It was formed by making tiny holes in it. For example, K. osaka et al.

IEEE Trang-Magn-NAG-21 by
(1985) p, IO2. In that case,
A conventional method of forming holes in an insulating layer by lift-off is shown in FIGS. 2(A) to (E), and a conventional method of forming holes in an insulating layer by etching is shown in FIGS. 3(A) to (F). show.

In the example of lift-off shown in Fig. 2 (A) to (E), Fig. 2 (
In A), first, a superconducting wiring layer 12 is placed on a substrate 11. In FIG. 2(B), a resist pattern 13 for a superconducting contact is formed on the superconducting wiring layer 12 by phosphorography technology. Next, as shown in FIG. 2(C), the superconducting wiring layer 12 is Then, an insulating layer 14 is deposited on the entire surface of the resist pattern 13. In FIG. 2 CD), the entire obtained intermediate is immersed in an organic solvent to remove the unnecessary insulating layer 14.
is removed together with the resist pattern 13 by lift-off. Next, in FIG. 2(E), a second superconducting wiring layer 15 is formed on the insulating layer 14.

In the etching examples shown in FIGS. 3(A) to 3(F), FIG.
In A), a superconducting wiring layer 22 is placed on a substrate 21, and then an insulating layer 24 is deposited on the entire surface of the superconducting wiring layer 22 as shown in FIG. 3(B). On this insulating layer 24,
As shown in FIG. 3(C), the resist pattern 23 of the superconducting contact I11 is formed by the phosphorography technique, and as shown in FIG. 3(D).

A portion of the insulating layer 24 is removed by etching using the resist pattern 23 as a mask. Next, Figure 3 (E)
The resist pattern 23 is removed as shown in FIG.
4, a second superconducting wiring layer 25 is formed.

Superconducting contacts formed by these methods are shown in Figure 2 (
E) or as shown in FIG.
When stacking another layer on Contact-F, the layer must be made thicker to avoid disconnections and breaks caused by such depressions.Therefore, there is a limit to the number of layers that can be stacked on Contact-F. there were. Furthermore, it is not possible to place Josephson junctions or device structures including them on conventional contacts, which has been an impediment to increasing integration density.

Furthermore, the resistance used in superconducting integrated circuits is typically 1
Since the thickness is about 1,000 mm, it could not be placed on conventional contacts. This is because the resistance value changes or the wire breaks at the step.

Furthermore, when constructing a three-dimensional integrated circuit,
In order to increase the integration density, it is desired to reduce the thickness of the wiring layer as much as possible.

[Problems to be Solved by the Invention] In view of these points, an object of the present invention is to provide a flat structure with no depressions above contacts to wiring in an integrated circuit such as a superconducting integrated circuit. An object of the present invention is to provide a method for manufacturing a contact for an integrated circuit, which can form a contact having a .

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first method on a substrate.
A superconducting wiring layer is placed, and a resist pattern is formed on the superconducting wiring layer to form a superconducting contact.
Etching is performed through the resist pattern to form a contact region, an insulating layer is disposed covering the resist pattern and the first superconducting wiring layer, the resist pattern and the insulating layer above the resist pattern are removed, and the insulating layer is etched. and a step of forming a second superconducting wiring layer on the exposed surface -L of the first superconducting wiring layer.

[Function] According to the present invention, it is possible to form a contact with a flat structure without a depression, so when a layer is stacked on the flat contact, the thickness of the layer can be particularly reduced. The number of stacked layers can be increased without increasing the thickness, and Josephson junctions or device structures including them can be placed on top of them, so the integration density of this type of integrated circuit can be greatly improved. I can do it.

[Example] The present invention will be described in detail below with reference to the drawings.

Figures 1 (A) to (H) show sequential steps in an embodiment of the present invention, where l is a substrate, 2 is a superconducting wiring layer disposed on the substrate 1, and 3 is for a superconducting contact. 4 is an insulating layer, and 5 is a flattening layer.

First, as shown in FIG. 1(A), a superconducting wiring layer 2 is deposited on a substrate l, and then, as shown in FIG. 1(B), a superconducting contact layer 2 is deposited on the superconducting wiring layer 2. Next, as shown in FIG. 1(C), using the resist pattern 3 as a mask, a part of the superconducting wiring layer 2 is removed by etching to form a contact. A region 2A is formed. Furthermore, Figure 1 (+
In step 1), an insulating layer 4 is deposited on the entire surface of the intermediate thus obtained, and the surface of the insulating layer 4 deposited on the portion of the superconducting wiring layer 2 that was previously removed by etching is removed. is made flush with the surface of the portion 2A of the superconducting wiring layer 2 that remains without being removed by etching. Next, in the step shown in FIG. 1(E), the entire obtained intermediate is immersed in an organic solvent, and the unnecessary first insulating layer 4 is removed together with the resist pattern 3 by lift-off. In this state, the insulating layer 4 and the contact region 2A are flush with each other. However, a groove 6 is formed between the two. Next, the first
In the process shown in FIG.
A leveling layer 5 of spin-on glass (SOG), organic silicon, or the like is deposited on the entire surface of A. Furthermore, Figure 1 (G)
As shown in FIG. 2, a portion 5A of the flattened layer 5 enters the groove 6 formed between the insulating layer 4 and the contact region 2A.
The planarization layer 5 is removed by etching to the top of the insulating layer 4 except for the following steps. This flattens the exposed surface. Finally, as shown in FIG. A second superconducting wiring layer 7 is deposited to form superconducting contacts.

[Effects of the Invention] As explained below, according to the present invention, it is possible to form a superconducting contact with a completely flat structure. The thickness can be made thinner than before, and multiple wiring layers can be stacked. Furthermore, since a Josephson junction or an element structure including the Josephson junction can be placed on the contact, the integration density can be increased compared to the conventional method.

[Brief explanation of drawings]

FIGS. 1(A) to (H) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(A) to (E) are cross-sectional views showing a conventional method using the lift-off method. FIGS. 3A to 3F are cross-sectional views showing a conventional method using etching. l... Substrate, 2.7... Superconducting wiring layer, 2A... Contact region, 3... Resist pattern. 4... Insulating layer, 5.5A... Flattening layer. 6...Groove. Designated Agent: Agency of Industrial Science and Technology, Electronics Technology Research Institute, Sato Roshi 2 Super-low ## Wiring layer 2A Contact 4 negative Doken A Fig. 1 2.7 (Fig. 1 12.15 Super im S delivery L1) 1 Fig. 2 23 Resist Jll" turn 24 Extremely rare layer Fig. 3 Special eyebrows!

Claims (1)

[Claims] 1) A first superconducting wiring layer is arranged on a substrate, a resist pattern for forming a superconducting contact is formed on the superconducting wiring layer, and a resist pattern is formed through the resist pattern. etching to form a contact region, disposing an insulating layer over the resist pattern and the first superconducting wiring layer, removing the resist pattern and the insulating layer on the resist pattern, and removing the insulating layer from the resist pattern and the first superconducting wiring layer; and forming a second superconducting wiring layer on the exposed surface of the first superconducting wiring layer. 2) A first superconducting wiring layer is placed on the substrate, a resist pattern for forming a superconducting contact is formed on the superconducting wiring layer, and etching is performed through the resist pattern to form a contact region. forming an insulating layer covering the resist pattern and the first superconducting wiring layer, removing the resist pattern and the insulating layer above the resist pattern, and removing the remaining insulating layer and the exposed first superconducting wiring layer.
a step of injecting a leveling agent into the groove between the insulating layer and the superconducting interconnect layer to form a second superconducting interconnect layer on the insulating layer and the exposed surface of the first superconducting interconnect layer; A method for manufacturing a contact for an integrated circuit, characterized by comprising: