JPH0260230B2 - - Google Patents
Info
- Publication number
- JPH0260230B2 JPH0260230B2 JP60195945A JP19594585A JPH0260230B2 JP H0260230 B2 JPH0260230 B2 JP H0260230B2 JP 60195945 A JP60195945 A JP 60195945A JP 19594585 A JP19594585 A JP 19594585A JP H0260230 B2 JPH0260230 B2 JP H0260230B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- superconducting layer
- josephson junction
- insulating layer
- superconducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000000470 constituent Substances 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 229910052758 niobium Inorganic materials 0.000 description 5
- 239000010955 niobium Substances 0.000 description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910000484 niobium oxide Inorganic materials 0.000 description 2
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はエツチングにより接合領域を規定する
トンネル型ジヨセフソン接合素子の製造方法に関
し、より詳しくは量子干渉計等、比較的厚い絶縁
層を有するジヨセフソン接合素子の製造方法に関
する。Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for manufacturing a tunnel-type Josephson junction device in which a junction region is defined by etching, and more particularly to a method for manufacturing a tunnel-type Josephson junction device that defines a junction region by etching. The present invention relates to a method for manufacturing a bonding element.
（従来技術）
従来例として、第３図にアイ・イー・イー・イ
ー・トランザクシヨン・オン・マグネテイクス第
19巻３号1983年827ページ（東海林他）（IEEE
TRANSACTIONS ON MAGNETICS、
vol19、No.3p827（1983））で発表されたジヨセフソ
ン接合素子の形成方法を示す。第３図Ａに示すよ
うに第１の超伝導層３１トンネル障壁層３２、第
２の超伝導層３３の接合構成層を形成した後フオ
トレジスト３４を用いたパターニングを行う。次
に第３図Ｂに示すように、前記フオトレジスト３
４をマスクにしてエツチングを行いジヨセフソン
接合領域以外の第２の超伝導体３３を除去し、ジ
ヨセフソン接合領域を規定する。その後第３図Ｃ
のように、第１の超伝導層３１と第３図Ｄに示す
第３の超伝導層３６との絶縁をとるための絶縁層
３５を被着する。前記フオトレジスト３４を用い
リフトオフを行いジヨセフソン接合、領域上の前
記絶縁層３５を除去した後、上部配線３６を被着
形成して第３図Ｄに示すジヨセフソン接合素子を
完成する。(Prior art) As a conventional example, FIG.
Volume 19, No. 3, 1983, page 827 (Tokairin et al.) (IEEE
TRANSACTIONS ON MAGNETICS,
vol 19, No. 3 p 827 (1983)). As shown in FIG. 3A, after forming the junction constituent layers of the first superconducting layer 31, tunnel barrier layer 32, and second superconducting layer 33, patterning is performed using a photoresist 34. Next, as shown in FIG. 3B, the photoresist 3
4 as a mask to remove the second superconductor 33 other than the Josephson junction region, thereby defining the Josephson junction region. Then Figure 3C
As shown in FIG. 3D, an insulating layer 35 is deposited to provide insulation between the first superconducting layer 31 and the third superconducting layer 36 shown in FIG. 3D. After lift-off is performed using the photoresist 34 to remove the insulating layer 35 on the Josephson junction region, an upper wiring 36 is deposited to complete the Josephson junction element shown in FIG. 3D.
（従来技術の問題点）
一例としてブリツジ型二接合量子干渉計を考え
る。ブリツジ型量子干渉計ではジヨセフソン接合
素子の上に絶縁層を介して、この量子干渉計に磁
界を与える制御線が形成される。このためジヨセ
フソン接合素子上面に段差があると、制御線に段
切れや制御線と第３の超伝導層３６との間の短絡
が生じる恐れがある。また、上記短絡を防ぐため
に、前記絶縁層を厚くすると、制御線と量子干渉
計との磁気的結合が弱くなる。このためこの量子
干渉計に用いるジヨセフソン接合素子は上面を平
坦にする必要がある。一方この量子干渉計では、
制御線との間の相互インダクタンスが、二つのジ
ヨセフソン接合素子間の絶縁層３５の断面積に比
例するので、集積度を上げるためには絶縁層３５
の膜厚を増加する必要がある。従来の製造方法で
は、絶縁層３５の膜厚が増加すると、ジヨセフソ
ン接合素子上面の平坦性を保つために、ジヨセフ
ソン接合領域を規定するエツチング深さも増加す
る必要があつた。このためエツチング深さの増加
に伴うパターン細りが著しくジヨセフソン接合寸
法の制御が難しかつた。また、前記エツチングに
反応性イオンエツチングを用いた場合、エツチン
グレートが周辺部と中央部で異なるため、エツチ
ング深さが増加するほど基板内でのジヨセフソン
接合寸法のばらつきが大きくなつていた。(Problems with the Prior Art) As an example, consider a bridge type two-junction quantum interferometer. In a bridge-type quantum interferometer, a control line that applies a magnetic field to the quantum interferometer is formed above the Josephson junction element via an insulating layer. Therefore, if there is a step on the upper surface of the Josephson junction element, there is a risk that a break in the control line or a short circuit between the control line and the third superconducting layer 36 may occur. Further, in order to prevent the short circuit, if the insulating layer is made thicker, the magnetic coupling between the control line and the quantum interferometer becomes weaker. Therefore, the Josephson junction element used in this quantum interferometer needs to have a flat top surface. On the other hand, in this quantum interferometer,
Since the mutual inductance between the control line and the control line is proportional to the cross-sectional area of the insulating layer 35 between two Josephson junction elements, the insulating layer 35 is
It is necessary to increase the film thickness. In conventional manufacturing methods, as the thickness of the insulating layer 35 increases, the etching depth that defines the Josephson junction region must also increase in order to maintain the flatness of the upper surface of the Josephson junction element. Therefore, as the etching depth increases, the pattern narrows significantly, making it difficult to control the dimensions of the Josephson junction. Further, when reactive ion etching is used for the etching, the etching rate is different between the peripheral portion and the central portion, so that as the etching depth increases, the variation in Josephson junction dimensions within the substrate increases.
このように、従来の製造方法では、ジヨセフソ
ン接合素子上面の平坦性と、絶縁層３５の膜厚の
増加の二つの要求を同時に満足した場合、ジヨセ
フソン接合寸法の制御性や均一性が損なわれると
いう欠点を有していた。 As described above, in the conventional manufacturing method, when the two requirements of flatness of the upper surface of the Josephson junction element and increase in the thickness of the insulating layer 35 are simultaneously satisfied, the controllability and uniformity of the Josephson junction dimensions are impaired. It had drawbacks.
（発明の目的）
本発明は、このような従来技術の欠点を取り除
いたジヨセフソン接合素子の製造方法を提供する
ことを目的としている。(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a Josephson junction device that eliminates the drawbacks of the prior art.
（発明の構成）
本発明によればトンネル型ジヨセフソン接合素
子の製造方法において、第１の超伝導層上にトン
ネル障壁層を介して第２の超伝導層が被着した接
合構成層を形成する工程と、少なくとも前記第２
の超伝導層を除去しかつ少なくとも前記第１の超
伝導層の磁場侵入深さに相当する膜厚を残すエツ
チングをジヨセフソン接合領域以外の前記接合構
成層に対して行いジヨセフソン接合領域を規定す
る工程と、前記エツチングにより残された前記接
合構成層上の前記ジヨセフソン接合領域以外の部
分に第１の絶縁層を形成する工程と、前記第２の
超伝導層および前記第１の絶縁上の前記ジヨセフ
ソン接合領域を覆う部分に第３の超伝導層を形成
する工程と、前記第２の超伝導層および前記第１
の絶縁層上の前記第３の超伝導層および前記第２
の絶縁層上に配線のための第４の超伝導層を形成
する工程を含むことを特徴とするジヨセフソン接
合素子の製造方法が得られる。(Structure of the Invention) According to the present invention, in the method for manufacturing a tunnel-type Josephson junction device, a junction constituent layer is formed in which a second superconducting layer is deposited on a first superconducting layer via a tunnel barrier layer. and at least the second
defining a Josephson junction region by performing etching on the junction constituent layers other than the Josephson junction region to remove the superconducting layer and leave a film thickness corresponding to at least the magnetic field penetration depth of the first superconducting layer; forming a first insulating layer on a portion of the junction component layer left by the etching other than the diosefson junction region; forming a third superconducting layer in a portion covering the bonding region;
the third superconducting layer on the insulating layer and the second superconducting layer on the insulating layer of
A method for manufacturing a Josephson junction device is obtained, which includes the step of forming a fourth superconducting layer for wiring on the insulating layer of the method.
（発明の詳細な説明）
本発明のジヨセフソン接合素子の製造方法にお
いてはジヨセフソン接合構成層と上部配線となる
第４の超伝導層の間に第３の超伝導層を形成する
工程を有している。この第３の超伝導層の存在に
より、ジヨセフソン接合領域を規定するエツチン
グの深さと、絶縁層の厚さを、ジヨセフソン接合
素子上面の平坦性を損なうことなしに独立に決め
ることができる。従つて、ジヨセフソン接合領域
を規定するエツチングの深さを必要最小限にする
ことができ、接合寸法の制御性や基板内での均一
性の良いジヨセフソン接合素子が得られる。(Detailed Description of the Invention) The method for manufacturing a Josephson junction element of the present invention includes the step of forming a third superconducting layer between the Josephson junction constituent layer and the fourth superconducting layer serving as an upper wiring. There is. The presence of this third superconducting layer allows the etching depth that defines the Josephson junction region and the thickness of the insulating layer to be determined independently without impairing the flatness of the top surface of the Josephson junction element. Therefore, the depth of etching that defines the Josephson junction region can be minimized, and a Josephson junction element with good controllability of junction dimensions and good uniformity within the substrate can be obtained.
（実施例）
本発明の実施例として第２図に示すブリツジ型
二接合量子干渉計の製造方法を示す。第１図は本
実施例の製造方法を説明するための図であり、第
２図に示す量子干渉計のうちジヨセフソン接合素
子部分が示してある。以下、第１図、第２図を用
いて本実施例を説明する。第１の超伝導層１１と
してニオブをスパツタにより200nｍ被着した後、
トンネルバリア層１２としてニオブ酸化膜を自然
酸化5nｍで成長させ、その上に第２の超伝導層
１３としてニオブを80nｍスパツタで被着し接合
構成層を形成する。次にフオトレジスト１４を用
いてパターニングを行い、CF4を用いた反応性イ
オンエツチングで100nｍの深さまでエツチング
を行い接合領域を規定する（第１図Ａ）。次に第
１の絶縁層１５としてSiOを100nｍ蒸着した後、
フオトレジスト１４を用いたリフトオフで接合領
域上のSiOを取り除く（第１図Ｂ）。続いてアル
ゴンガスを用いたスパツタクリーニングで接合領
域上の酸化物や不純物を除去した後第３の超伝導
層１７としてニオブを400nｍスパツタで被着す
る。その後フオトレジスト１６を用いてパターニ
ングを行い、CF4を用いた反応性イオンエツチン
グで、接合領域を覆う部分を残して第３の超伝導
層を除去する（第１図Ｃ）。その後、第２の絶縁
層１８を400nｍ蒸着した後、フオトレジスト１
６を用いたリフトオフを行い、第３の超伝導層１
７上の第２の絶縁層を取り除く。アルゴンガスを
用いたスパツタクリーニングで、第３の超伝導層
１７上のニオブ酸化物や不純物を除去した後、第
４の超伝導層１９としてニオブを200nｍを被着
する。第４の超伝導層１９上にフオトレジストを
用いてパターニングを行い、CF4を用いた反応性
イオンエツチングで、第４の超伝導層１９の不要
な部分を除去し、このジヨセフソン接合素子の上
部配線とする（第１図Ｄ）。(Example) As an example of the present invention, a method for manufacturing a bridge type two-junction quantum interferometer shown in FIG. 2 will be described. FIG. 1 is a diagram for explaining the manufacturing method of this embodiment, and shows the Josephson junction element portion of the quantum interferometer shown in FIG. 2. This embodiment will be explained below using FIG. 1 and FIG. 2. After depositing 200 nm of niobium as the first superconducting layer 11 by sputtering,
A niobium oxide film is grown with a natural oxidation thickness of 5 nm as the tunnel barrier layer 12, and 80 nm of niobium is sputtered thereon as the second superconducting layer 13 to form a junction constituting layer. Next, patterning is performed using photoresist 14, and etching is performed to a depth of 100 nm using reactive ion etching using CF 4 to define a bonding region (FIG. 1A). Next, after depositing SiO to a thickness of 100 nm as the first insulating layer 15,
SiO on the junction area is removed by lift-off using photoresist 14 (FIG. 1B). Subsequently, oxides and impurities on the bonding region are removed by sputter cleaning using argon gas, and then 400 nm of niobium is deposited as the third superconducting layer 17 by sputtering. Thereafter, patterning is performed using photoresist 16, and reactive ion etching using CF 4 is performed to remove the third superconducting layer, leaving a portion covering the junction area (FIG. 1C). After that, after depositing the second insulating layer 18 to a thickness of 400 nm, a photoresist 1
Lift-off using 6 is performed to form the third superconducting layer 1
Remove the second insulating layer on 7. After removing niobium oxide and impurities on the third superconducting layer 17 by sputter cleaning using argon gas, a 200 nm thick layer of niobium is deposited as the fourth superconducting layer 19. Patterning is performed using photoresist on the fourth superconducting layer 19, and unnecessary portions of the fourth superconducting layer 19 are removed by reactive ion etching using CF 4 to form the upper part of this Josephson junction element. Wiring (Figure 1D).
このジヨセフソン接合素子が二つ並んだ基板上
（第２図）に第３の絶縁層２１としてSiO膜を
100nｍ蒸着した後、第５の超伝導層２２として
ニオブを200nｍスパツタで被着し、フオトレジ
ストでパターニングを行い、CF4を用いた反応性
イオンエツチングで加工、成形する。以上示した
工程を経て、第２図に示す二接合のブリツジ型量
子干渉計を製造する。なお第５の超伝導層２２は
この量子干渉計に磁界を与える制御線である。 A SiO film is deposited as the third insulating layer 21 on the substrate on which the two Josephson junction elements are arranged (Fig. 2).
After evaporating 100 nm, 200 nm of niobium is sputtered as the fifth superconducting layer 22, patterned with photoresist, processed and molded by reactive ion etching using CF 4 . Through the steps described above, the two-junction bridge type quantum interferometer shown in FIG. 2 is manufactured. Note that the fifth superconducting layer 22 is a control line that applies a magnetic field to this quantum interferometer.
本実施例で示した本発明の製造方法を用いれ
ば、第３の超伝導層１７の厚さを調節すること
で、第３の絶縁層１８との段差を解消し、上面を
平坦に保つことできる。そのため接合構成層のエ
ツチングは絶縁層の厚さに関係なく必要最小限す
ることができ、ジヨセフソン接合寸法の制御性や
基板内での均一性を下げることなく回路の集積度
を上げることができる。本実施例では従来例に比
べ接合構成層のエツチング深さが５分の１になつ
ている。 By using the manufacturing method of the present invention shown in this example, by adjusting the thickness of the third superconducting layer 17, it is possible to eliminate the level difference with the third insulating layer 18 and keep the top surface flat. can. Therefore, the etching of the bonding layer can be kept to a minimum regardless of the thickness of the insulating layer, and the degree of circuit integration can be increased without reducing the controllability of Josephson bonding dimensions or the uniformity within the substrate. In this embodiment, the etching depth of the bonding layer is one-fifth that of the conventional example.
（発明の効果）
以上説明したように、本発明の製造方法を用い
れば、接合構成層と上部配線の間の絶縁層の厚さ
に関係なく、接合構成層のエツチング深さを必要
最小限にすることができるので、厚い前記絶縁層
を用いた場合でも、接合寸法の制御性や基板内で
の均一性の良いジヨセフソン接合素子が得られ
る。(Effects of the Invention) As explained above, by using the manufacturing method of the present invention, the etching depth of the bonding layer can be reduced to the necessary minimum regardless of the thickness of the insulating layer between the bonding layer and the upper wiring. Therefore, even when the thick insulating layer is used, a Josephson junction element with good controllability of junction dimensions and good uniformity within the substrate can be obtained.
第１図は、本発明によるジヨセフソン接合素子
の製造方法を説明するための図、第２図は、実施
例による量子干渉計の断面図、第３図は、従来の
製造方法を示すための図である。
図において、１１……第１の超伝導層、１２…
…トンネル障壁層、１３……第２の超伝導層、１
４……フオトレジスト、１５……第１の絶縁層、
１６……フオトレジスト、１７……第３の超伝導
層、１８……第２の絶縁層、１９……第４の超伝
導層、２１……第３の絶縁層、２２……第５の超
伝導層、３１……第１の超伝導層、３２……トン
ネル障壁層、３３……第２の超伝導層、３４……
フオトレジスト、３５……絶縁層、３６……第３
の超伝導層。
FIG. 1 is a diagram for explaining the method for manufacturing a Josephson junction device according to the present invention, FIG. 2 is a cross-sectional view of a quantum interferometer according to an embodiment, and FIG. 3 is a diagram for explaining a conventional manufacturing method. It is. In the figure, 11...first superconducting layer, 12...
...Tunnel barrier layer, 13...Second superconducting layer, 1
4... Photoresist, 15... First insulating layer,
16... Photoresist, 17... Third superconducting layer, 18... Second insulating layer, 19... Fourth superconducting layer, 21... Third insulating layer, 22... Fifth Superconducting layer, 31... First superconducting layer, 32... Tunnel barrier layer, 33... Second superconducting layer, 34...
Photoresist, 35... Insulating layer, 36... Third
superconducting layer.
Claims (1)
において、第１の超伝導層上にトンネル障壁層を
介して第２の超伝導層が被着した接合構成層を形
成する工程と、少なくとも前記第２の超伝導層を
除去しかつ少なくとも前記第１の超伝導層の磁場
侵入深さに相当する膜厚を残すエツチングをジヨ
セフソン接合領域以外の前記接合構成層に対して
行いジヨセフソン接合領域を規定する工程と、前
記エツチングにより残された前記接合構成層上の
前記ジヨセフソン接合領域以外の部分に第１の絶
縁層を形成する工程と、前記第２の超伝導層およ
び前記第１の絶縁層上の前記ジヨセフソン接合領
域を覆う部分に第３の超伝導層を形成する工程
と、前記第２の超伝導層および前記第１の絶縁層
上の前記第３の超伝導層以外の部分に第２の絶縁
層を形成する工程と、前記第３の超伝導層および
前記第２の絶縁層上に配線のための第４の超伝導
層を形成する工程を含むことを特徴とするジヨセ
フソン接合素子の製造方法。1. A method for manufacturing a tunnel-type Josephson junction device, comprising: forming a junction constituent layer in which a second superconducting layer is deposited on the first superconducting layer via a tunnel barrier layer; defining a Josephson junction region by performing etching on the junction constituent layers other than the Josephson junction region to remove the conductive layer and leave a film thickness corresponding to at least the magnetic field penetration depth of the first superconducting layer; forming a first insulating layer on a portion of the junction component layer left by the etching other than the Josephson junction region; and forming a Josephson junction on the second superconducting layer and the first insulating layer. forming a third superconducting layer in a portion covering the region; and forming a second insulating layer in a portion other than the third superconducting layer on the second superconducting layer and the first insulating layer. and forming a fourth superconducting layer for wiring on the third superconducting layer and the second insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60195945A JPS6257262A (en) | 1985-09-06 | 1985-09-06 | Manufacture of josephson junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60195945A JPS6257262A (en) | 1985-09-06 | 1985-09-06 | Manufacture of josephson junction element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6257262A JPS6257262A (en) | 1987-03-12 |
| JPH0260230B2 true JPH0260230B2 (en) | 1990-12-14 |
Family
ID=16349584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60195945A Granted JPS6257262A (en) | 1985-09-06 | 1985-09-06 | Manufacture of josephson junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6257262A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234533A (en) * | 1987-03-24 | 1988-09-29 | Agency Of Ind Science & Technol | Formation of josephson junction element |
| JPH0831628B2 (en) * | 1990-06-22 | 1996-03-27 | 工業技術院長 | Josephson integrated circuit fabrication method |
-
1985
- 1985-09-06 JP JP60195945A patent/JPS6257262A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6257262A (en) | 1987-03-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |