JPS6377176A - Manufacture of josephson junction device - Google Patents
Manufacture of josephson junction deviceInfo
- Publication number
- JPS6377176A JPS6377176A JP61222408A JP22240886A JPS6377176A JP S6377176 A JPS6377176 A JP S6377176A JP 61222408 A JP61222408 A JP 61222408A JP 22240886 A JP22240886 A JP 22240886A JP S6377176 A JPS6377176 A JP S6377176A
- Authority
- JP
- Japan
- Prior art keywords
- film
- superconductor
- forming
- josephson junction
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000002887 superconductor Substances 0.000 claims abstract description 57
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010955 niobium Substances 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔ａ要〕
本発明のジョセフソン接合素子の製造方法は、支持基板
上の第１の超伝導体膜」−に第１の絶縁１りを形成し、
該第１の絶縁膜に開口部を設けてその上に順次、第２の
超伝導体膜、トンネルバリア膜および第３の超伝導体膜
を形成し、更に該第３の超伝導体膜の上にレジスト膜を
形成し、その後、エッチバック法により前記レジスト膜
、第３の超伝導体膜、トンネルバリア膜、第２の超伝導
体膜および第１の絶縁膜をエツチングして、該第１の絶
縁膜の開口部の中に第２の超伝導体膜、トンネルパリア
膜、第３の超伝導体膜および第２の絶縁膜を埋め込んだ
構造にし、次いで第１の絶縁膜およびレジスＩＩＰＪを
マスクとし前記開口部の中の第２の超伝導体膜、トンネ
ルバリア膜および第３の超伝導体膜のエツジ部分を酸化
して酸化膜を形成し、次に前記開口部の中のレジスト膜
を除去した後、全面に配線用膜を形成することを特徴と
する。[Detailed Description of the Invention] [a] A method for manufacturing a Josephson junction element of the present invention includes forming a first insulator on a first superconductor film on a support substrate,
An opening is provided in the first insulating film, a second superconductor film, a tunnel barrier film, and a third superconductor film are sequentially formed thereon; A resist film is formed thereon, and then the resist film, the third superconductor film, the tunnel barrier film, the second superconductor film, and the first insulating film are etched by an etch-back method. A second superconductor film, a tunnel parrier film, a third superconductor film, and a second insulating film are embedded in the opening of the first insulating film, and then the first insulating film and the resist IIPJ are buried. using as a mask, oxidize the edge portions of the second superconductor film, tunnel barrier film, and third superconductor film in the opening to form an oxide film, and then remove the resist in the opening. The method is characterized in that after the film is removed, a wiring film is formed on the entire surface.
本発明によれば前記エツジ部分に酸化膜を形成している
ので、第３の超伝導体膜と配線用膜とをコンタクトする
ためのコンタクトホールを形成する必要がない、このた
め従来のコンタクトホール形成時に見込んでいた位置合
わせ余裕は不要となり、極めて小面積のジョセフソン接
合素子を製造することが可ずｔとなるので、素子の高速
化、高性濠化かつ高集積化を図ることができる。According to the present invention, since an oxide film is formed on the edge portion, there is no need to form a contact hole for contacting the third superconductor film and the interconnection film, and therefore the conventional contact hole is not required. The alignment margin that was expected during formation is no longer necessary, and it becomes impossible to manufacture a Josephson junction element with an extremely small area, making it possible to achieve higher speed, higher performance, and higher integration of the element. .
本発明はジョセフソン接合素子の製造方法に関する。 The present invention relates to a method of manufacturing a Josephson junction device.
高速の論理回路やメモリ回路あるいは検知素子等に使用
する場合、素子面積が小さく寄生容量の少ないジョセフ
ソン接合妻子が要求されている。When used in high-speed logic circuits, memory circuits, sensing elements, etc., Josephson junctions with small device area and low parasitic capacitance are required.
第２図は従来のジョセフソン接合素子を形成する製造工
程を説明する図である。従来の製造方法によれば、まず
Ｓ＋基板２１を熱酸化して５１２ｗ２２２を形成し１次
にＷｂかうなる下部電極用の超伝導体膜２３．アルニウ
ム／アルミニウム酸化膜の複合部からなるトンネルバリ
ア［２４，Ｎｂからなる上部電極用の超伝導体膜２５お
よびレジスト膜２６を順次形成する０次いでパターニン
グされたレジスト膜２６をマスクとして超伝導体膜２５
、トンネルバリア膜２４．超伝導体膜２３をドライエツ
チングして下部電極としての超伝導体膜２３のパターニ
ングを行う（同図（ａ））。FIG. 2 is a diagram illustrating a manufacturing process for forming a conventional Josephson junction element. According to the conventional manufacturing method, the S+ substrate 21 is first thermally oxidized to form 512w222, and then the superconductor film 23 for the lower electrode made of Wb is formed. A tunnel barrier made of a composite part of an aluminum/aluminum oxide film [24], a superconductor film 25 for the upper electrode made of Nb and a resist film 26 are sequentially formed.Next, the superconductor film is formed using the patterned resist film 26 as a mask. 25
, tunnel barrier film 24. The superconductor film 23 is dry-etched to pattern the superconductor film 23 as a lower electrode (FIG. 4(a)).
次にパターニングされた別のレジスト膜２７をマスクと
して超伝導体膜２５．トンネルバリア膜２４および超伝
導体膜２３の一部をエツチングすることにより、接合領
域を定める（同図（ｂ） ） 。Next, using another patterned resist film 27 as a mask, the superconductor film 25. By etching a portion of the tunnel barrier film 24 and superconductor film 23, a junction region is defined (FIG. 2(b)).
次いで層間絶縁膜としてのＳ１２！ｉ ２７を全面に形
成した後に該５ｉＯ２ｔｌｕ２７にコンタクト用の開口
部を設け、更にＮｂからなる配線用膜２８を被着した後
にパターニングすることにより、同図（Ｃ）に示すよう
なジョセフソン接合素子を形成することができる。Next, S12 as an interlayer insulating film! After forming the i27 on the entire surface, a contact opening is provided in the 5iO2tlu27, and a wiring film 28 made of Nb is further deposited and patterned to form a Josephson junction element as shown in FIG. can be formed.
ところで従来例の製造方法によれば、第２図（ｂ）に示
すように、小面積のジョセフソン接合素子を形成するた
めにはレジスＮＩＱ２７（７）パターニングを出来るだ
け小さく行う必要があるが、ある程度以上小さくなると
レジストａの現像工程時に該レジスト膜が剥離してしま
い、高い歩留まりで製造することができないという問題
がある。By the way, according to the conventional manufacturing method, as shown in FIG. 2(b), in order to form a Josephson junction element with a small area, it is necessary to pattern the resist NIQ27(7) as small as possible. If the resist film becomes smaller than a certain level, the resist film will peel off during the development process of resist a, and there is a problem that manufacturing with a high yield cannot be achieved.
また従来例の！ａＪ＆方法によれば超伝導体膜２５の上
の絶縁膜２７にコンタクト用の開口部を設ける必要があ
るので、超伝導体膜２５の大きさは該開口部の大きさに
このときの位置合わせズレの余裕を加えたものになり、
接合面積の小さいジョセフソン接合素子を形成すること
が困難となっている。Another conventional example! According to the aJ & method, it is necessary to provide an opening for contact in the insulating film 27 on the superconductor film 25, so the size of the superconductor film 25 is aligned at this time with the size of the opening. It has added margin for misalignment,
It has become difficult to form a Josephson junction element with a small junction area.
本発明はかかる従来の問題点に鑑みて創作されたもので
あり、接合面積の小さいジョセフソン接合妻子の提供を
目的とする。The present invention was created in view of such conventional problems, and an object of the present invention is to provide a Josephson jointed wife and child having a small joint area.
本発明はジョセフソン接合素子の製造方法は支持基板上
に第１の超伝導体膜を形成する工程と。A method of manufacturing a Josephson junction device according to the present invention includes a step of forming a first superconductor film on a support substrate.
前記第１の超伝導体膜上に第１の絶縁膜を形成し、該第
１の絶縁膜に開口部を設ける工程と、前記第１の絶縁膜
の上に順次、第２の超伝導体膜。forming a first insulating film on the first superconductor film and providing an opening in the first insulating film; and sequentially forming a second superconductor on the first insulating film. film.
トンネルバリア膜および第３の超伝導体膜を形成する工
程と、前記第３の超伝導体膜の上にレジスト膜を形成す
る工程と、エッチバック法により前記レジスト膜、第３
の超伝導体膜、トンネルバリア膜、第２の超伝導体膜お
よび第１の絶縁膜をエツチングして、該第１の絶縁膜の
開口部の中に第２の超伝導体膜、トンネルバリア膜、第
３の超伝導体膜および第２の絶縁膜を埋め込んだ構造に
する工程と、前記第１の絶縁膜およびレジスト膜をマス
クとし前記開口部の中の第２の超伝導体膜、トンネルバ
リア膜および第３の超伝導体膜のエツジ部分を酸化して
酸化膜を形成する工程と、前記開口部の中のレジスト膜
を除去する工程と、全面に配線用膜を形成した後に該配
線用膜をパターニングする工程とを有することを特徴と
する。a step of forming a tunnel barrier film and a third superconductor film; a step of forming a resist film on the third superconductor film; and a step of forming a resist film and a third superconductor film by an etch-back method.
The superconductor film, the tunnel barrier film, the second superconductor film, and the first insulating film are etched to form a second superconductor film, a tunnel barrier film in the opening of the first insulating film. a second superconductor film in the opening using the first insulating film and the resist film as a mask; A step of oxidizing the edge portions of the tunnel barrier film and the third superconductor film to form an oxide film, a step of removing the resist film in the opening, and a step of forming the wiring film on the entire surface, and then forming an oxide film. The method is characterized by comprising a step of patterning a wiring film.
本発明によれば、エッチバック法により最初のパターニ
ングによって形成された第１の絶縁膜の開口部の中に３
層構造（第２の超伝導体膜−トンネルバリア膜−第３の
超伝導体膜）のジョセフソン接合素子を埋め込み、かつ
その開口部の中心にスペーサとしての第２の絶縁膜を設
ける。これにより該３層構造のエッヂ部分のみに酸化膜
を形成することができるので、コンタクト用の開口部を
設けることなく第３の超伝導体膜と配線用の超伝導体膜
とをコンタクトさせることができる。このようにコンタ
クトを形成する場合の位１合わせズレを見込む必要がな
いので、接合面積の極めて小さなジョセフソン接合素子
を製造することができる。According to the present invention, three layers are formed in the opening of the first insulating film formed by the first patterning using the etch-back method.
A Josephson junction element having a layered structure (second superconductor film-tunnel barrier film-third superconductor film) is buried, and a second insulating film as a spacer is provided at the center of the opening. As a result, the oxide film can be formed only on the edge portion of the three-layer structure, so that the third superconductor film and the wiring superconductor film can be brought into contact without providing an opening for contact. Can be done. In this way, since there is no need to take into account a one-dimensional misalignment when forming a contact, a Josephson junction element with an extremely small junction area can be manufactured.
次に図を参照しながら本発明の実施例について説明する
。第１図は本発明の実施例に係るジョセフソン接合素子
の製造工程を説明する断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating the manufacturing process of a Josephson junction device according to an embodiment of the present invention.
（１）まずＳ＋基板ｌを熱酸化してｓ、ｏ２膜２を形成
することにより支持基板を形成し、更に超伝導体膜であ
る膜厚２００ｎｍのＮｂからなる下部電極３を形成した
後に該下部電極３をパターニングする（同図（＆））。(1) First, a supporting substrate is formed by thermally oxidizing the S+ substrate l to form an s, o2 film 2, and then a lower electrode 3 made of Nb with a thickness of 200 nm, which is a superconductor film, is formed. The lower electrode 3 is patterned ((&) in the same figure).
（２）次に膜厚６００ｎｍの５ｉＴｏＴｆ！Ｊからなる
絶縁膜４をスパッタ法により被着した後に、パターニン
グを行って開口部５を形成する（同図（ｂ））。(2) Next, 5iToTf with a film thickness of 600 nm! After an insulating film 4 made of J is deposited by sputtering, patterning is performed to form openings 5 (FIG. 4(b)).
（３）次に膜厚２００ｎｍのＮｂからなる超伝導体膜６
．膜厚８ｎｍのＡ文膜を堆積した後に、該Ａｎ膜の表面
を酸化してＡｉｍ／Ａ！；Ｌ酸化膜からなるトンネルバ
リア膜７を形成する。続いてＮｂからなる超伝導体！Ｉ
８を全面に被着する（同図（Ｃ） ） 。(3) Next, a superconductor film 6 made of Nb with a film thickness of 200 nm
．． After depositing an A film with a thickness of 8 nm, the surface of the An film is oxidized to form Aim/A! ; Form a tunnel barrier film 7 made of an L oxide film. Next is a superconductor made of Nb! I
8 on the entire surface (see figure (C)).
（４）その後ＡＺ１３５０Ｊ （商標名）レジスト膜９
をスピナーにより全面にコーティングする（同図（ｄ）
）。(4) Then AZ1350J (trade name) resist film 9
Coat the entire surface with a spinner ((d) in the same figure)
).
（５）次いで（：Ｆ４＋３０％０２ガスでドライエツチ
ングする。このときレジスト膜９とＮｂ ’Ｂ （超伝
導体１１Ｑ６ 、８）のエッチレートをほぼ等しくする
ことができるので表面が平坦化する。エツチングは三層
構造（超伝導体膜６−ドンンネルバリア膜７−超伝導体
！Ｉ８）のエツジ部分が露出したところで停止する（同
図（ｅ））。(5) Next, dry etching is performed using (:F4+30%02 gas).At this time, the etching rate of the resist film 9 and Nb'B (superconductor 11Q6, 8) can be made almost equal, so that the surface is flattened.Etching stops when the edge portion of the three-layer structure (superconductor film 6 - tunnel barrier film 7 - superconductor!I8) is exposed (FIG. 2(e)).
（６）次に絶縁１ｇｌおよび開口部の中心に残っている
レジスト膜９をマスクとして陽極酸化を行い。(6) Next, anodic oxidation is performed using the insulation 1gl and the resist film 9 remaining at the center of the opening as a mask.
露出している三層構造のエッヂ部分に膜厚５０ｎｍのＮ
ｂ２Ｏ５ｇ！からなる酸化膜１０を形成する（同図（ｆ
））。A 50 nm thick N layer is applied to the exposed edge of the three-layer structure.
b2O5g! An oxide film 10 consisting of
)).
（７）その後、レジスト膜９を除去する（同図（ｇ）
） 。(7) After that, the resist film 9 is removed ((g) in the same figure).
).
（８）次いで全面に膜厚７００ｎｍのＮｂ膜を形成した
後にパターニングして配線用ｌ１２１１を形成すること
によりジョセフソン接合素子が完成する（同図（ｈ））
。(8) Next, a Nb film with a thickness of 700 nm is formed on the entire surface and then patterned to form a wiring layer 1211, thereby completing a Josephson junction element ((h) in the same figure).
.
このように本発明の実施例方法によれば、開口部５の中
に三層構造の接合部を埋め込むのでその接合面積を極め
て小さくすることができる。As described above, according to the method of the embodiment of the present invention, since the three-layer bonding portion is embedded in the opening 5, the bonding area can be made extremely small.
またスペーサとしてのレジスト膜９を陽極酸化のマスク
として利用し、酸層構造のエッヂ部分のみを酸化するこ
とができる。このため配線用膜１１と超伝導体膜８とを
マスクによる位を合ゎせを行うことなくコンタクトさせ
ることができるので、より接合面積の小さなジョセフソ
ン接合素子を形成することができる。Further, by using the resist film 9 as a spacer as a mask for anodic oxidation, only the edge portions of the acid layer structure can be oxidized. Therefore, the wiring film 11 and the superconductor film 8 can be brought into contact without alignment using a mask, so that a Josephson junction element with a smaller junction area can be formed.
なお実施例ではＮｂＷｉを用いたが、本発明はＮｂ Ｎ
膜（窒化ニオブ膜）など、他の超伝導体膜を用いた場合
にも適用できることは勿論である。Although NbWi was used in the embodiment, the present invention uses NbN
Of course, the present invention can also be applied to cases where other superconductor films such as a niobium nitride film are used.
以上説明したように、本発明の製造方法によればジョセ
フソン接合素子の接合面積は第１の絶縁膜に設けた開口
部の大きさによって一義的に定めることができるので、
接合面積を極めて小さくすることができる。このため高
速で高性能、かつ高集植度のジョセフソン接合素子を製
造することができる。As explained above, according to the manufacturing method of the present invention, the junction area of the Josephson junction element can be uniquely determined by the size of the opening provided in the first insulating film.
The bonding area can be made extremely small. Therefore, it is possible to manufacture a Josephson junction element with high speed, high performance, and high density.
第１図は本発明の実施例に係るジョセフソン接合素子の
製造工程を説明する断面図、
第２図は従来例のジョセフソン接合素子の製造工程を説
明する断面図である。
（符号の説明）
１・・・３１基板、
２・・・３１ｏｚＪｇ！、
３・・・下部電極（ＮｂＩｇｉ）
４・・・絶縁膜（Ｓｉ ０２膜）、
６．８・・・超伝導体膜（Ｎｂ膜）。
７・・・トンネルバリア膜（ＡｆＬ／Ａ文酸化膜）、９
・・・レジスト膜、
ｌＯ・・・酸化膜（Ｎｂ２０ｓ膜）。
１１・・・配線用膜（Ｎｂ ′ｆｌＪ） 。FIG. 1 is a sectional view illustrating the manufacturing process of a Josephson junction element according to an embodiment of the present invention, and FIG. 2 is a sectional view illustrating the manufacturing process of a conventional Josephson junction element. (Explanation of symbols) 1...31 board, 2...31ozJg! , 3... Lower electrode (NbIgi) 4... Insulating film (Si 02 film), 6.8... Superconductor film (Nb film). 7... Tunnel barrier film (AfL/A oxide film), 9
...Resist film, lO... Oxide film (Nb20s film). 11... Wiring film (Nb'flJ).
Claims (1)
１の絶縁膜に開口部を設ける工程と、前記第１の絶縁膜
の上に順次、第２の超伝導体膜、トンネルバリア膜およ
び第３の超伝導体膜を形成する工程と、 前記第３の超伝導体膜の上にレジスト膜を形成する工程
と、 エッチバック法により前記レジスト膜、第３の超伝導体
膜、トンネルバリア膜、第２の超伝導体膜および第１の
絶縁膜をエッチングして、該第１の絶縁膜の開口部の中
に第２の超伝導体膜、トンネルバリア膜、第３の超伝導
体膜および第２の絶縁膜を埋め込んだ構造にする工程と
、前記第１の絶縁膜およびレジスト膜をマスクとし前記
開口部の中の第２の超伝導体膜、トンネルバリア膜およ
び第３の超伝導体膜のエッジ部分を酸化して酸化膜を形
成する工程と、 前記開口部の中のレジスト膜を除去する工程と、 全面に配線用膜を形成した後に該配線用膜をパターニン
グする工程とを有することを特徴とするジョセフソン接
合素子の製造方法。[Claims] A step of forming a first superconductor film on a support substrate, forming a first insulating film on the first superconductor film, and forming an opening in the first insulating film. forming a second superconductor film, a tunnel barrier film, and a third superconductor film in sequence on the first insulating film; and the third superconductor film. forming a resist film thereon; etching the resist film, the third superconductor film, the tunnel barrier film, the second superconductor film, and the first insulating film by an etch-back method; forming a structure in which a second superconductor film, a tunnel barrier film, a third superconductor film, and a second insulating film are embedded in the opening of the first insulating film; oxidizing edge portions of the second superconductor film, the tunnel barrier film, and the third superconductor film in the opening using the film and the resist film as masks to form an oxide film; 1. A method for manufacturing a Josephson junction element, comprising the steps of: removing a resist film therein; and forming a wiring film over the entire surface, and then patterning the wiring film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61222408A JPS6377176A (en) | 1986-09-19 | 1986-09-19 | Manufacture of josephson junction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61222408A JPS6377176A (en) | 1986-09-19 | 1986-09-19 | Manufacture of josephson junction device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6377176A true JPS6377176A (en) | 1988-04-07 |
Family
ID=16781910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61222408A Pending JPS6377176A (en) | 1986-09-19 | 1986-09-19 | Manufacture of josephson junction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6377176A (en) |
-
1986
- 1986-09-19 JP JP61222408A patent/JPS6377176A/en active Pending
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