JPS63307787A - Manufacture of josephson circuit - Google Patents
Manufacture of josephson circuitInfo
- Publication number
- JPS63307787A JPS63307787A JP62143746A JP14374687A JPS63307787A JP S63307787 A JPS63307787 A JP S63307787A JP 62143746 A JP62143746 A JP 62143746A JP 14374687 A JP14374687 A JP 14374687A JP S63307787 A JPS63307787 A JP S63307787A
- Authority
- JP
- Japan
- Prior art keywords
- inductance
- josephson
- electrode
- junctions
- lower electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 abstract 3
- 239000006185 dispersion Substances 0.000 abstract 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 13
- 238000007796 conventional method Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000010955 niobium Substances 0.000 description 6
- 229910052758 niobium Inorganic materials 0.000 description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
ジョセフソン接合を多接合にしたジョセフソン回路の製
造において、
下部電極を厚い領域と薄い領域からなるように形成して
その段差部の側面に絶縁膜を形成することにより、
相隣る接合の分離間隙の短小化を容易にさせたものであ
る。[Detailed Description of the Invention] [Summary] In manufacturing a Josephson circuit with multiple Josephson junctions, a lower electrode is formed to consist of a thick region and a thin region, and an insulating film is formed on the side surface of the stepped portion. By doing so, the separation gap between adjacent joints can be easily shortened.
本発明は、ジョセフソン接合を多接合にしたジョセフソ
ン回路の製造方法に関す。The present invention relates to a method for manufacturing a Josephson circuit using multiple Josephson junctions.
上記のジョセフソン回路は、相醸に分離された複数のジ
ョセフソン接合に対して下部電極および上部電極を共通
にしたものであり、相隣る接合の分離間隙がインダクタ
ンスを形成するものである。The Josephson circuit described above has a lower electrode and an upper electrode in common for a plurality of mutually separated Josephson junctions, and the separation gap between adjacent junctions forms an inductance.
このため、上記分離間隙は、所望の大きさに製造出来る
ようになることが望まれる。Therefore, it is desired that the separation gap can be manufactured to a desired size.
第３図は、ジョセフソン接合を多接合にしたジョセフソ
ン回路の製造の従来方法を説明する（縛す断面図である
。FIG. 3 is a cross-sectional view illustrating a conventional method for manufacturing a Josephson circuit using multiple Josephson junctions.
同図において、先ず、スパッタ堆積、およびレジストマ
スクを用いたパターン化エツチングで、基扱１−トに下
部電極２を形成する。In the figure, first, a lower electrode 2 is formed on a substrate 1 by sputter deposition and patterned etching using a resist mask.
次いで、スパッタ堆積で絶縁膜５を形成し、しシストマ
スクを用いたパターン化エツチングで絶縁膜５にｇなる
間隙を設けて二つの接合窓６を形成する。Next, an insulating film 5 is formed by sputter deposition, and two bonding windows 6 are formed in the insulating film 5 with a gap of g by patterned etching using a cyst mask.
次いで、スパッタ堆積などで接合窓６の底面および絶縁
膜５の表面にトンネルバリア層３を形成する。Next, a tunnel barrier layer 3 is formed on the bottom surface of the junction window 6 and the surface of the insulating film 5 by sputter deposition or the like.
次いで、スパッタ堆積、およびレジストマスクを用いた
パターン化エツチングで上部電極４を形成し、更に上部
電極４の外側に表出したトンネルバリア層３を除去する
。Next, the upper electrode 4 is formed by sputter deposition and patterned etching using a resist mask, and the tunnel barrier layer 3 exposed outside the upper electrode 4 is removed.
かくして、接合窓６の底面部にジョセフソン接合が形成
され、間隙ｇを接合の分離間隙とする２接合のジョセフ
ソン回路が出来上がる。In this way, a Josephson junction is formed at the bottom of the junction window 6, and a two-junction Josephson circuit is completed with the gap g serving as the separation gap between the junctions.
そして、この分離間隙は、先に述べたように、インダク
タンスを形成し、このインダクタンスを小さくする場合
には、分離間隙即ち接合窓６の間隙ｇを小さくすれば良
い。As described above, this separation gap forms an inductance, and in order to reduce this inductance, the separation gap, that is, the gap g between the bonding windows 6 can be made small.
しかしながら、上述した従来の製造方法では、間隙ｇが
接合窓６形成の際のエツチングに用いるレジストマスク
のパターン寸法に依存しているため、インダクタンスの
ばらつきを少なくするように精度を確保して間隙ｇを小
さくすることには実用的に限度があって、間隙ｇを例え
ば２μｍ以下にすることが極めて困難である。However, in the conventional manufacturing method described above, the gap g depends on the pattern dimensions of the resist mask used for etching when forming the bonding window 6, so accuracy is ensured to reduce variations in inductance. There is a practical limit to reducing the gap g, and it is extremely difficult to reduce the gap g to, for example, 2 μm or less.
ｃ問題点を解決するための手段〕
上記問題点は、ジョセフソン接合の下部電極を厚い領域
と薄い領域からなるように形成してその段差部の側面に
絶縁膜を形成し、しかる後、トンネルバリア層と上部電
極を形成して、ジョセフソン接合を段差部で分離された
多接合にする本発明の製造方法によって解決される。Measures for Solving Problem c] The above problem can be solved by forming the lower electrode of the Josephson junction to consist of a thick region and a thin region, forming an insulating film on the side surface of the stepped portion, and then forming a tunnel. This problem is solved by the manufacturing method of the present invention, in which a barrier layer and an upper electrode are formed to form Josephson junctions into multiple junctions separated by step portions.
本発明方法により製造されたジョセフソン回路は、上記
段差の大きさと上記絶縁膜の厚さの和が、従来方法の場
合の間隙ｇに相当して分離間隙となりインダクタンスを
形成する。In the Josephson circuit manufactured by the method of the present invention, the sum of the size of the step and the thickness of the insulating film becomes a separation gap corresponding to the gap g in the conventional method and forms an inductance.
そして、その段差の大きさおよび絶縁膜の厚さは、何れ
も通常の加工方法で精度良り０．１μｍオーダにするこ
とが容易である。The size of the step and the thickness of the insulating film can both be easily made to the order of 0.1 μm with good precision using normal processing methods.
従って、本発明方法によれば、従来方法の場合より分離
間隙の短小化が容易になり、インダクタンスの小さな然
もそのばらつきの少ない多接合のジョセフソン回路を製
造することが可能になる。Therefore, according to the method of the present invention, it is easier to shorten the separation gap than in the case of the conventional method, and it becomes possible to manufacture a multi-junction Josephson circuit with small inductance and less variation.
以下本発明方法の二つの実施例についていて第１図およ
び第２図の１程順側断面図を用いて説明する。Two embodiments of the method of the present invention will be described below using forward sectional views of FIGS. 1 and 2.
第一の実施例は以下の如くである。即ち、第１図におい
て、
先ず〔図（ａｌ参照〕、基板１１上にニオブ（Ｎｂ）を
３０００人の厚さにスパッタ堆積し、レジストマスク２
１をマスクにした異方性エツチングここではＲＩＥ
（反応性イオンエツチング）でパターン化エツチングし
て、下部電極１２のパターンを形成する。The first embodiment is as follows. That is, in FIG. 1, first, niobium (Nb) is sputter deposited on the substrate 11 to a thickness of 3000 mm, and then a resist mask 2 is formed.
Anisotropic etching using 1 as a mask Here, RIE
Patterned etching is performed using (reactive ion etching) to form a pattern for the lower electrode 12.
レジストマスク２１はその後除去する。Resist mask 21 is then removed.
次いで〔図（ｂ）参照〕、下部電極計のパターンの両側
の領域を表出させたレジストマスク２２をマスクにし、
その表出領域を２０００人の深さにＲＴＥでエフチン、
グ除去して１０００人の厚さに残し、ニオブの厚い領域
と薄い領域からなり段差部１７を有する下部電極１２を
形成する。レジストマスク２２はその後除去する。Next [see figure (b)], a resist mask 22 exposing the regions on both sides of the pattern of the lower electrode meter is used as a mask,
Evchin with RTE to the depth of 2000 people,
The niobium layer is removed to leave a thickness of 1,000 niobium, and a lower electrode 12 having a stepped portion 17 is formed of a thick region and a thin region of niobium. Resist mask 22 is then removed.
次いで〔図ｔＣ１参照〕、全面に二酸化シリコンの一ヒ
面が全て表出するまでエツチングして、下部電極針の段
差部１７の側面およびパターンの側面に二酸化シリコン
の絶縁ｌｌ！１１５を形成する。段差部１７の絶縁膜１
５の厚さ （図の横方向）は略２０００人となる。Next, [see Figure tC1], etching is performed until the entire surface of silicon dioxide is exposed, and silicon dioxide is insulated on the side surface of the stepped portion 17 of the lower electrode needle and the side surface of the pattern! 115 is formed. Insulating film 1 of step portion 17
The thickness of 5 (horizontal direction in the figure) is approximately 2,000 people.
次いで〔図ｆｄ）参照〕、下部電極１２の表出面をアル
ゴン（Ａｒ）などでスパッタクリーニングしてから、ア
ルミ三つム（ＡＩ）を２０人にスパッタ堆積し、それを
アルゴン＋酸素（０２）で酸化して酸化アルミニウム（
ＡＩＯう）のトンネルバリア層１３を形成し、更に、ニ
オブを３０００人の厚さにスパッタ堆積してパターン化
前の上部電極１４を形成する。Next, [see Figure FD], the exposed surface of the lower electrode 12 is sputter-cleaned with argon (Ar), etc., and then aluminum trimming (AI) is sputter-deposited on 20 layers, and then it is mixed with argon + oxygen (02). to form aluminum oxide (
A tunnel barrier layer 13 of AIO is formed, and niobium is sputter deposited to a thickness of 3000 nm to form an upper electrode 14 before patterning.
次いで〔図（ｅｌ参照〕、レジストマスク２３をマスク
にしたＲＩＥでパターン化前の上部電極１４をパターン
化エツチングして、下部電極１２の全てを覆うニオブの
上部電極１４を形成し、更に上部電極１４の外側に表出
したトンネルバリアＪｉｔ１３を除去する。Next, as shown in FIG. The tunnel barrier Jit 13 exposed outside the tunnel barrier Jit 14 is removed.
レジストマスク２３はその後除去する。The resist mask 23 is then removed.
かくして、下部電極１２の厚い領域と薄い領域のそれぞ
れの上面部にジョセフソン接合が形成され、各接合の間
が段差部１７で分離された３接合のジョセフソン回路が
出来上がる。Thus, Josephson junctions are formed on the upper surface of each of the thick and thin regions of the lower electrode 12, and a three-junction Josephson circuit is completed in which each junction is separated by a stepped portion 17.
このジョセフソン回路は、段差部１７における段差の大
きさと絶縁膜１５の厚さとの和が、従来方法の場合の間
隙ｇに相当して接合の分離間隙となりインダクタンスを
形成するが、この分離間隙が略０．４μｍとなって間隙
ｇの短小化限度より遥かに小さいので、インダクタンス
が従来方法の場合より極めて小さくなる。In this Josephson circuit, the sum of the size of the step in the step portion 17 and the thickness of the insulating film 15 corresponds to the gap g in the conventional method, and becomes the separation gap of the junction, forming an inductance. Since it is approximately 0.4 μm, which is much smaller than the limit for reducing the gap g, the inductance is much smaller than that in the conventional method.
然も、上述の工程から判るように、分離間隙となるト記
和の大きさは精度良く制御可能であるので、インダクタ
ンスのばらつきが少ない。However, as can be seen from the above-mentioned process, the size of the gap serving as the separation gap can be controlled with high precision, so there is little variation in inductance.
第二の実施例は以下の如くである。即ち、第２図におい
て、
先ず〔図（ａ）参照〕、第一の実施例の場合と同様にし
て、第１図（ｄ）までの工程即ちパターン化前の上部電
極１４の形成までを行う。この際、下部電極１２は横並
びに配列して複数にする。The second embodiment is as follows. That is, in FIG. 2, first [see FIG. 2(a)], the steps up to FIG. 1(d), that is, the formation of the upper electrode 14 before patterning, are performed in the same manner as in the first embodiment. . At this time, a plurality of lower electrodes 12 are arranged side by side.
次いで〔図中）参照〕、レジストマスク２４をマスクに
したＲＩＥでパターン前の上部電極１４をパターン化エ
ツチングして、相隣る下部電極１２の間に跨りパターン
の縁が下部電極１２の中央部に位置する上部電極１４ａ
を形成し、更に一ヒ部電極１４ａの外側に表出したトン
ネルバリア層１３を除去する。レジストマスク２４はそ
の後除去する。Next, as shown in the figure, the upper electrode 14 before the pattern is patterned and etched by RIE using the resist mask 24 as a mask, so that the edge of the pattern straddles between the adjacent lower electrodes 12 and the edge of the pattern is at the center of the lower electrode 12. The upper electrode 14a located at
is formed, and then a portion of the tunnel barrier layer 13 exposed to the outside of the part electrode 14a is removed. Resist mask 24 is then removed.
かくして、下部電極１２の一つに２組の２接合が形成さ
れて、各々の２接合の組が直列に接続されたジョセフソ
ン回路が出来上がる。Thus, two sets of 2-junctions are formed on one of the lower electrodes 12, and a Josephson circuit is completed in which each set of 2-junctions is connected in series.
このジョセフソン回路においても、インダクタンスを形
成する分離間隙が第一の実施例と同様になるので、イン
ダクタンスは、従来方法の場合より極めて小さくなり、
且つそのばらつきが少ない。In this Josephson circuit as well, the separation gap that forms the inductance is the same as in the first embodiment, so the inductance is much smaller than in the conventional method.
Moreover, the variation is small.
なお、上述の実施例において、下部電極１２および上部
電極１４．１４ａを窒化ニオブ（ＮｂＮ）などで形成し
ても良いこと、更には、パターン化にリフトオフ法を採
用して上部電極を鉛（Ｐｂ）合金で形成しても良いこと
は容易に類推されよう。In the above embodiment, the lower electrode 12 and the upper electrode 14.14a may be formed of niobium nitride (NbN) or the like, and furthermore, the lift-off method is adopted for patterning and the upper electrode is formed of lead (PbN). ) It can be easily inferred that it may be formed of an alloy.
以上説明したように本発明の構成によれば、ジョセフソ
ン接合を多接合にしたジョセフソン回路の製造において
、相隣る接合の分離間隙の短小化を容易にさせることが
可能になり、その分離間隙が形成するインダクタンスを
ばらつきを抑えて小さくすることを可能にさせる効果が
ある。As explained above, according to the configuration of the present invention, in manufacturing a Josephson circuit with multiple Josephson junctions, it is possible to easily shorten the separation gap between adjacent junctions, and the separation This has the effect of suppressing variations in the inductance formed by the gap and making it possible to reduce it.
第１図は本発明方法の第一の実施例の工程順側断面図、
第２図は第二の実施例の工程順側断面図、第３図は従来
方法を説明する側断面図、である。
図において、
１．１１は基板、
２．１２は下部電極、
３．１３はトンネルバリア層、
４．１４．１４ａは一ヒ部電極、
５．１５は絶縁膜、
６は接合窓、
１７は段差部、
２１〜２４はレジストマスク、
である。
−一゛
峯二の実施夕Ｊｃ？）１狂１１功イ９“１印面聞手 ２
図
ｆえ１牙、オ赤１と、＝ごン二日月りるイ９′コｉ山５
ｒ：ａ早 ３ 図FIG. 1 is a step-by-step sectional view of the first embodiment of the method of the present invention, FIG. 2 is a step-by-step side sectional view of the second embodiment, and FIG. 3 is a side sectional view explaining the conventional method. be. In the figure, 1.11 is the substrate, 2.12 is the lower electrode, 3.13 is the tunnel barrier layer, 4.14.14a is the partial electrode, 5.15 is the insulating film, 6 is the junction window, and 17 is the step. Parts 21 to 24 are resist masks. - Ichimine 2 implementation evening Jc? ) 1 crazy 11 go 9 “1 seal face listener 2
Figure f 1 Fang, O Red 1, = Gon Nikazuki Rirurui 9' Koi Mountain 5
r: a early 3 figure
Claims (1)
らなるように形成してその段差部の側面に絶縁膜を形成
し、しかる後、トンネルバリア層と上部電極を形成して
、ジョセフソン接合を段差部で分離された多接合にする
ことを特徴とするジョセフソン回路の製造方法。The lower electrode of the Josephson junction is formed to consist of a thick region and a thin region, and an insulating film is formed on the side surface of the stepped portion.After that, a tunnel barrier layer and an upper electrode are formed to form the Josephson junction with the stepped portion. A method for manufacturing a Josephson circuit characterized by forming a multi-junction separated by sections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62143746A JPS63307787A (en) | 1987-06-09 | 1987-06-09 | Manufacture of josephson circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62143746A JPS63307787A (en) | 1987-06-09 | 1987-06-09 | Manufacture of josephson circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63307787A true JPS63307787A (en) | 1988-12-15 |
Family
ID=15346051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62143746A Pending JPS63307787A (en) | 1987-06-09 | 1987-06-09 | Manufacture of josephson circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63307787A (en) |
-
1987
- 1987-06-09 JP JP62143746A patent/JPS63307787A/en active Pending
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