JPS61140184A - Manufacture of josephson ic - Google Patents

Abstract

PURPOSE:To enable clean window-boring without burrs by a method wherein a thin film of Ce or Si is kept provided beneath the insulation film such as an SiO2 film as the stopper, and RIE is carried out under the condition to exclusively etch this insulation film; thereafter, sputter etching is carried out under the condition to exclusively etch the stopper. CONSTITUTION:An insterlayer insulation film 11 is formed on a ground plane 10 typically made of Nb. Further, an Nb base electrode 12 is formed thereon, and next a Ge film 13 and an SiO film 14 are formed by continuous evaporation. Then, these are coated with a resist 15, and the resist at the junction forming part is removed in stripe form, where RIE is carried out at a gas pressure of 15mTorr and a high frequency output of 100W by using CHF3 as the reactive gas. Under this condition etching stops in the state of leaving the Ge film. Successively, the exposed Ge film is removed by sputter etching with Ar gas. Since the Ge film is thin and the processing film is short, the etching amount of the SiO film 11 is small, and windows can be bored by leaving the sufficiently thick SiO film 11. Use of Si in place of Ge enables the same processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a method of manufacturing integrated circuits including Josephson devices, and more particularly to a method of avoiding excessive etching of interlayer dielectrics.

Logic circuits using Josephson elements operate at high speed and consume extremely little power, so they have great potential for realizing ultra-high density integrated circuits for large-scale computers.
Research and development is underway.

Figure 3 shows a typical pattern of a Josephson element formed in a Josephson integrated circuit;
is a plan view, and FIG.

A region 32 indicated by a broken line in FIG. 3(a) is the base electrode of the Josephson element, and a counter electrode 37 is formed thereon. These two electrodes are in contact with each other via a bonding film 39 at a bonding portion 38, and an interlayer insulating film 34 is interposed between them at other portions. Furthermore, a ground brain 30 exists below these through an insulating film 31 of the same type as the interlayer insulating film 34.

The materials of the two electrodes and the ground brain are superconductors such as Nb or PB gold alloy, and a Josephson device is a device in which these are combined via a bonding film. Since this is not a hindrance, but is concerned exclusively with the method of realizing such a structure, the following is explained below.
Only the structure will be explained.

Such a structure is made by sputtering a Nb film on an insulating film and patterning it to form a base electrode, then depositing an interlayer insulating film to open a window in the bonding area, and then depositing a Pb alloy again. They are formed in the order of forming the counter electrode. The bonding film is formed at an appropriate time before forming the counter electrode, but it is an extremely thin film of, for example, Nb oxide, and does not affect the implementation conditions of the present invention, so it will not be discussed in the following explanation. do not have.

[Conventional technology]

This is carried out by opening a window in the bonding portion by lifting off or by reactive ion etching (hereinafter abbreviated as RIE).

In the lift-off method, a resist is applied to the junction formation area on the Nb film that will serve as the base electrode, an insulating material such as SiO is deposited, and the resist is removed, thereby forming an interlayer insulating film and opening a window at the junction area all at once. In this case, it is possible to realize the structure of FIG. 3 using a striped window called a half window.

This method requires less man-hours and is self-aligned, making it possible to achieve high integration. However, it has the disadvantage that it tends to cause cracks in the area where lift-off is performed. This occurs because the part of the deposited SiO on the resist and other parts are not completely discontinuous, and it is difficult to completely eliminate this even if the resist pattern is made into an overhang structure. . The presence of the wires causes problems such as disconnection of the wiring later.

On the other hand, in the method of opening a window using RIB, after forming an interlayer insulating film, the entire surface except the junction formation portion is masked with resist, and RIE is performed to open the window for junction formation. Although this method does not generate paris, half windows cannot be used, and a mask pattern in which each window is independent, called a full window, as shown in FIG. 4, must be used.

After forming the interlayer insulating film, if RTE is performed using a half-window mask, etching will not proceed any further in the area where the Nb base electrode exists below, as long as the Nb surface is exposed. In places where there is no Nb base electrode, such as the part 99 in FIG. 3(b), etching proceeds without stopping, and the insulating film on the ground plane is also etched. If RIB is performed to such an extent that the ground plane is completely formed, there is a risk that a portion of the ground brain will be exposed, which will hinder the formation of an integrated circuit. Therefore, a half-window mask cannot be used in this method.

When a full window is used, the cell area is approximately 20% larger than that of a self-aligned half window, and the degree of integration is reduced accordingly. If a half-window type mask can be used for opening windows by RIE, the degree of integration can be improved.

[Problem that the invention seeks to solve]

The present invention provides a method of opening a window by dry etching using a half-window type mask, which has been difficult to implement with the prior art.

[Means for solving problems]

The above-mentioned problems are solved by the method of the present invention as described in the claims section, but to summarize according to the embodiments described below, the present invention solves the problem by using SiO or SiO which functions as an interlayer insulating film. ! A thin film of Ge or Si is provided as a stopper under the insulating film, and after opening a window in the insulating film by performing RYE under conditions that exclusively etch the insulating film, the stopper is etched exclusively. The stopper window is opened by sputter etching under the following conditions.

[Effect]

In the method of the present invention, RIE on the interlayer insulating film almost stops progressing after opening the window in the target layer, so a half window type mask is used to perform the RIE.
You can open the window with E.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of the present invention, which corresponds to the process of realizing the structure shown in FIG. 3.

FIG. 1(a) shows a state in which an interlayer insulating film 11 is formed on a ground brain 10, which is typically Nb, and an Nb base electrode 12 is further formed on it. It is formed by thermally oxidizing the surface of a Si substrate, but the substrate portion is omitted in the figure.

First, as shown in Fig. 1(b), the thickness of SOO person G
The E film 13 and the SiO film 14 having a thickness of 3,000 wafers are formed by continuous vapor deposition. Although Ge is a semiconductor at room temperature, it can be considered an insulator at the low temperatures at which Josephson devices operate.
An interlayer insulating film is formed by these two layers.

Next, a resist 15 is applied thereon, and the resist in the bond forming portion is removed in stripes. This state is shown in FIG. 1(c), but since this figure is a cross-sectional view, the stripes extend perpendicularly to the plane of the paper.

For this, CHF s was used as the reactive gas, and the gas pressure was 1
RIE is performed at 5 mm Torr and a high frequency output of 100 W (target area 250 mmφ). Under these conditions, the SiO film is etched at a rate of 300 people/win, while the Ge film is etched at a rate of 75 people/win. It is. Therefore, regardless of the presence or absence of the base voltage $1112, G
Etching can be stopped with the e-film remaining. This state is shown in FIG. 1(d).

In addition to CHF3, CzFh is used as a reactive gas.

Cs F s or CF4 mixed with H2 can be used, and S i O! can be used as an insulating material. This kind of processing is also possible when using .

Subsequently, the exposed Ge film is removed by sputter etching using Ar gas (FIG. 1(e)).

This can be carried out continuously using the same apparatus used for RIE, and the processing conditions are, for example, a high frequency output of 80 W and a gas pressure of 10 mTorr. Under these conditions, the etching rate of the Ge film is 105 people/l1in;
That of the SiO film is 60 people/win, but because the Ge film is small and the processing time is short, the amount of SiO film 11 etched is small, and the etching rate is 60 people/win.
It is possible to open the window while leaving Ill. Similar processing is possible when 3i is used instead of Ge.

Thereafter, by forming the counter electrode 17 as shown in FIG. 1(f), the structure shown in FIG. 3 is realized.

Figure 2? -'A second embodiment of the present invention is shown.

This is an application of the present invention to the interlayer connection of superconductor wiring formed in two layers, and as shown in FIG. After depositing the SiO film 24, a through hole is opened under the same processing conditions as in the above embodiment, and a second superconductor wiring 27 is formed by sputtering, thereby realizing an interlayer connection as shown in FIG. 2(b). You can.

〔Effect of the invention〕

As mentioned above, according to the method of the present invention, it is possible to selectively dry-etch the interlayer dielectric film of a Josephson integrated circuit without excessively etching it, so that it can be etched without paris by using a half-window type mask. You can open beautiful windows.

The present invention has made it possible to increase the degree of integration of Josephson integrated circuits.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing embodiments of the present invention, FIG. 3 is a view showing the structure of a Josephson integrated circuit, and FIG. 4 is a view showing a full window type mask pattern. 10.30 is the ground brain 11.14.21, 24, 31.34 is the SiO film 12.
32 is a base electrode 13 of a Josephson element. 23 is Ge
The film 15 is the resist 17.37 is the counter electrode 26.2 of the Josephson element.
7 is a superconductor wiring 38, a junction portion 39 of a Josephson element, a bonding film 99, and a groove. 1st Senan 1 Figure (e) 阜2cause. Leno 9

Claims (3)

[Claims] (1) The process of sequentially depositing two types of materials with different dry etching resistance characteristics to form an interlayer insulating film, and the etching rate for the first material constituting the interlayer insulating film constitute the interlayer insulating film. dry etching the first material of the interlayer insulating film under processing conditions that are higher than the etching rate for the second material layer, and then dry etching the first material of the interlayer dielectric film under process conditions such that the etching rate for the second material is higher than the etching rate for the second material layer adjacent below the second material layer; dry etching the second material of the interlayer insulating film under processing conditions that are higher than the etching rate for both the underlying layer material and the first material. Production method. (2) Among two materials having different dry etching resistance characteristics, the first material is silicon dioxide or silicon monoxide, and the second material is germanium or silicon, and the 2. A method of manufacturing a Josephson integrated circuit as claimed in claim 1, further comprising depositing a first material. (3) Reactive ion etching is performed on the first material using CHF_3, C_2F_6, C_3F_4, or CF_4/H_2 as a reactive gas, and sputter etching is performed on the second material using Ar gas. A method of manufacturing a Josephson integrated circuit according to claim 2.