JPS63117468A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63117468A JPS63117468A JP26427786A JP26427786A JPS63117468A JP S63117468 A JPS63117468 A JP S63117468A JP 26427786 A JP26427786 A JP 26427786A JP 26427786 A JP26427786 A JP 26427786A JP S63117468 A JPS63117468 A JP S63117468A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate electrode
- gate
- semiconductor substrate
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title description 9
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000001020 plasma etching Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にプラズマエ
ツチング法を用いてゲート電極を形成する工程を有する
MOS型の半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device including a step of forming a gate electrode using a plasma etching method.
従来、この種の半導体装置の製造方法は、半導体素子の
ゲート電極を形成する場合、ウェブI・エツチング法ま
たはドライエツチング法が用いられるが、ウェットエツ
チング法はパターン寸法の制御性が悪いという欠点があ
ることがら、最近の高集積度化した半導体素子の形成に
おいてはドライエツチング法が用いられ、ながでもサイ
ドエッチが少く、ゲート電極材料とゲート絶縁膜との選
択比がすぐれたプラズマエツチング法が多く用いられて
いる。Conventionally, in the manufacturing method of this type of semiconductor device, when forming the gate electrode of a semiconductor element, a web I etching method or a dry etching method is used, but the wet etching method has the disadvantage of poor controllability of pattern dimensions. For some reason, recent dry etching methods are used in the formation of highly integrated semiconductor devices, while plasma etching methods, which cause less side etching and have an excellent selectivity between the gate electrode material and the gate insulating film, are preferred. It is often used.
上述した従来の半導体装置の製造方法は、プラズマエツ
チング法によりゲート電極を形成する方法となっている
ので、エツチング中にゲート電極に電荷が蓄えられ、こ
の電荷がエツチング処理が終ると同時にゲート絶縁膜を
通して半導体基板に流れ、ゲート絶縁膜を破壊し特性不
良になることが多いという欠点がある。この現象は、ゲ
ート絶縁膜の膜圧が500人より薄い高集積度化した半
導体装置において多く発生する。In the conventional semiconductor device manufacturing method described above, the gate electrode is formed by plasma etching, so that charge is accumulated in the gate electrode during etching, and this charge is transferred to the gate insulating film as soon as the etching process is completed. The drawback is that it often flows through the semiconductor substrate and destroys the gate insulating film, resulting in poor characteristics. This phenomenon often occurs in highly integrated semiconductor devices where the film thickness of the gate insulating film is less than 500 nm.
本発明の目的は、ゲート絶縁膜の破壊を防止することが
でき、不良率を低減することができる半導体装置の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent breakdown of a gate insulating film and reduce the defect rate.
本発明の半導体装置の製造方法は、半導体基板上にゲー
ト絶縁膜とこのゲート絶縁膜に続くフィールド絶縁膜と
を形成した後、前記ゲート絶縁膜に近接した前記フィー
ルド絶縁膜の一部を開口して前記半導体基板に達する開
口部を形成する工程と、前記ゲート絶縁膜、フィールド
絶縁膜及び開口部の各表面に電極層を形成する工程と、
前記電極層をプラズマエツチング法によ選択的にエツチ
ングし、ゲート電極とこのゲート電極に接続しかつ前記
開口部を介して前記半導体基板に接続する放電電極部と
を形成する工程と、前記ゲート電極と前記放電電極部と
を切断し絶縁する工程とを有している。The method for manufacturing a semiconductor device of the present invention includes forming a gate insulating film and a field insulating film following the gate insulating film on a semiconductor substrate, and then opening a part of the field insulating film close to the gate insulating film. forming an opening reaching the semiconductor substrate; forming an electrode layer on each surface of the gate insulating film, the field insulating film, and the opening;
selectively etching the electrode layer by a plasma etching method to form a gate electrode and a discharge electrode portion connected to the gate electrode and connected to the semiconductor substrate via the opening; and a step of cutting and insulating the discharge electrode portion.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの製造工程順に示した半導体装置の断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor device shown in the order of manufacturing steps for explaining one embodiment of the present invention.
まず、第1図(a)に示すように、半導体基板1上にL
OCO3法により酸化膜のゲート絶縁膜2とこのゲート
絶縁膜2に続くフィールド絶縁膜3とを形成した後、ゲ
ート絶縁膜2に近接したフィールド絶縁膜3の一部に、
ホトレジストをマスクとしてプラズマエツチング法によ
り半導体基板1に達するまで開口して開口部4を形成す
る。First, as shown in FIG. 1(a), an L is placed on a semiconductor substrate 1.
After forming an oxide gate insulating film 2 and a field insulating film 3 following this gate insulating film 2 by the OCO3 method, a part of the field insulating film 3 adjacent to the gate insulating film 2 is
Using photoresist as a mask, an opening 4 is formed by plasma etching until the semiconductor substrate 1 is reached.
次に、第1図(b)に示すように、ゲート絶縁膜2.フ
ィールド絶縁膜3及び開口部4の各表面にCVD法によ
り多結晶シリコンの電極層5を形成する。Next, as shown in FIG. 1(b), the gate insulating film 2. An electrode layer 5 of polycrystalline silicon is formed on each surface of the field insulating film 3 and the opening 4 by CVD.
次に、第1図(c)に示すように、ホトレジストをマス
クとしてプラズマエツチング法によりゲート電極6と、
このゲート電極6に接続しかつ開口部4を介して半導体
基板1と接続する放電電極部7とを形成する。Next, as shown in FIG. 1(c), the gate electrode 6 is etched by plasma etching using a photoresist as a mask.
A discharge electrode portion 7 is formed to be connected to the gate electrode 6 and to the semiconductor substrate 1 via the opening 4.
続いて、第1図(d)に示すように、ホトレジストをマ
スクとしてウェットエツチング法によりゲート電極6と
放電電極部7とを切断、分離し、これらを電気的に絶縁
する。Subsequently, as shown in FIG. 1(d), the gate electrode 6 and the discharge electrode portion 7 are cut and separated by a wet etching method using a photoresist as a mask to electrically insulate them.
この方法によると、ゲート電極6が放電電極部7により
半導体基板1と導通して形成されるので、プラズマエツ
チング中にゲート電極6に電荷が蓄積されず、ゲート絶
縁膜1の破壊を防止することができる。According to this method, the gate electrode 6 is formed to be electrically connected to the semiconductor substrate 1 through the discharge electrode portion 7, so that no charge is accumulated in the gate electrode 6 during plasma etching, and breakdown of the gate insulating film 1 can be prevented. Can be done.
なお、第1図において、開口部4はフィールド絶縁膜3
の一部を薄くし開口しやすくして形成されているが、薄
くせずに開口してもよい。Note that in FIG. 1, the opening 4 is the field insulating film 3.
Although a part of the opening is made thinner to make it easier to open, the opening may be made without making it thinner.
第2図はゲート絶縁膜3に対する破壊電界強度の度数分
布を示す特性図である。FIG. 2 is a characteristic diagram showing the frequency distribution of the breakdown electric field strength for the gate insulating film 3.
第2図に示すように、本実施例によるゲート絶縁膜3の
破壊電界強度は低いところには無く、0 、7〜0 、
9 M V / cmの狭い範囲に集中して分布してい
るのに対し、従来例によるものは低いところから多く分
布し、本実施例による効果の大きいことが分る。As shown in FIG. 2, the breakdown electric field strength of the gate insulating film 3 according to this example is not low, and is 0,7~0,
The distribution is concentrated in a narrow range of 9 MV/cm, whereas the conventional example has a large distribution starting from a low range, which shows that the effect of this example is large.
第3図は半導体装置の不良率と歩留りとの関係を示す特
性図である。FIG. 3 is a characteristic diagram showing the relationship between defective rate and yield of semiconductor devices.
第3図に示すように、本実施例によると、同一の歩留り
であっても不良率は著しく低下する。As shown in FIG. 3, according to this embodiment, even if the yield remains the same, the defective rate is significantly reduced.
以上説明したように本発明は、ゲート電極をプラズマエ
ツチング法により形成する際に、ゲート電極を放電電極
部により半導体基板と導通させながら形成することによ
り、ゲート絶縁膜の破壊を防止することができ、不良率
を低減することができる効果がある。As explained above, in the present invention, when forming the gate electrode by plasma etching, the gate electrode is formed while being electrically connected to the semiconductor substrate through the discharge electrode portion, thereby making it possible to prevent damage to the gate insulating film. This has the effect of reducing the defective rate.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの製造工程順に示した半導体装置の断面図、第2図は
ゲート絶縁膜に対する破壊電界強度の度数分布を示す特
性図、第3図は半導体装置の不良率と歩留りとの関係を
示す特性図である。
1・・・半導体基板、2・・・ゲート絶縁膜、3・・・
フィールド絶縁膜、4・・・開口部、5・・・電極層、
6・・・ゲート電極、7・・・放電電極部、8・・・切
断部。
万1目FIGS. 1(a) to (d) are cross-sectional views of a semiconductor device shown in the order of manufacturing steps to explain one embodiment of the present invention, and FIG. 2 is a characteristic showing the frequency distribution of breakdown electric field strength with respect to the gate insulating film. 3 are characteristic diagrams showing the relationship between defective rate and yield of semiconductor devices. 1... Semiconductor substrate, 2... Gate insulating film, 3...
field insulating film, 4... opening, 5... electrode layer,
6... Gate electrode, 7... Discharge electrode part, 8... Cutting part. 10,000 eyes
Claims (1)
くフィールド絶縁膜とを形成した後、前記ゲート絶縁膜
に近接した前記フィールド絶縁膜の一部を開口して前記
半導体基板に達する開口部を形成する工程と、前記ゲー
ト絶縁膜、フィールド絶縁膜及び開口部の各表面に電極
層を形成する工程と、前記電極層をプラズマエッチング
法により選択的にエッチングし、ゲート電極とこのゲー
ト電極に接続しかつ前記開口部を介して前記半導体基板
に接続する放電電極部とを形成する工程と、前記ゲート
電極と前記放電電極部とを切断し絶縁する工程とを有す
ることを特徴とする半導体装置の製造方法。After forming a gate insulating film and a field insulating film following the gate insulating film on a semiconductor substrate, a part of the field insulating film close to the gate insulating film is opened to form an opening that reaches the semiconductor substrate. a step of forming an electrode layer on each surface of the gate insulating film, the field insulating film and the opening, and selectively etching the electrode layer by a plasma etching method to connect the gate electrode to the gate electrode. and a step of forming a discharge electrode portion connected to the semiconductor substrate through the opening, and a step of cutting and insulating the gate electrode and the discharge electrode portion. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26427786A JPS63117468A (en) | 1986-11-05 | 1986-11-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26427786A JPS63117468A (en) | 1986-11-05 | 1986-11-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63117468A true JPS63117468A (en) | 1988-05-21 |
Family
ID=17400933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26427786A Pending JPS63117468A (en) | 1986-11-05 | 1986-11-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63117468A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03178136A (en) * | 1989-12-06 | 1991-08-02 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US6274921B1 (en) | 1997-12-22 | 2001-08-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit including protective transistor protecting another transistor during processing |
-
1986
- 1986-11-05 JP JP26427786A patent/JPS63117468A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03178136A (en) * | 1989-12-06 | 1991-08-02 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US6274921B1 (en) | 1997-12-22 | 2001-08-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit including protective transistor protecting another transistor during processing |
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