JPH03178136A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the electrostatic breakdown of a gate dielectric film to the charging phenomenon of a film to be machined by forming an electrical contact between the conductive film to be machined having an electric contact with a gate electrode and a region having the same conductivity type as a substrate section oppositely faced to the gate electrode. CONSTITUTION:Electric contacts 15a, 15b are shaped between a conductive film to be machined 7 having an electric contact with a gate electrode 5a and a region having the same conductivity type as a substrate section 10 opposite to a gate electrode 5b. Consequently, the charged particles of the film to be machined 7 can be flowed out to the outside of a substrate. Accordingly, the addition of a manufacturing treatment process, the prolongation of a treating time, etc., are unnecessitated completely only by adding a number of mask patterns, and the electrostatic breakdown of gate dielectric films 6a, 6b to the charging of the film to be machined 7 by the shock of charged particles at the time of dry etching treatment, etc., without having any effect on the performance of a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having an MO3 structure.

[Conventional technology]

FIG. 2(al) and (C) are a plan view and a cross-sectional view showing the structure of a conventional CMOS transistor.
FIG. 7A is a plan view showing a state in which the pattern formation of the second layer wiring is completed. Figure 2(b) is II of Figure 2(a).
-II line sectional view, showing the cross section at the time of starting the etching process for forming the pattern of the second layer wiring.

In FIG. 2, 1 is an isolated silicon oxide film, 2 is an n-type low concentration diffusion region (hereinafter referred to as "n- region"), and 3 is a p-type
4 is a type fovea concentration diffusion region (hereinafter referred to as "p" region), 4 is an n-type high concentration diffusion region (hereinafter referred to as "rn"region)>,
5a is the first layer wiring that becomes the gate electrode of the p-channel transistor, 5b is the first layer wiring that becomes the gate electrode of the n-channel transistor, 6a is the gate silicon oxide film of the p-channel transistor, and 6b is the gate of the n-channel transistor. 1 is a silicon oxide film, 7 is a second layer wiring which is a film to be etched (film to be processed), 8 is a contact between first and second layer wiring, 9 is a silicon oxide film which is an insulating film between the eyebrows, 1
0 is a p-type silicon substrate, 11 is a contact between the second layer wiring 7 and the p+ region 3, and 12 is a contact between the second layer wiring 7 and n+hl
Contact with region 4, 13 indicates a resist pattern, and 14 indicates ion incidence during dry etching.

Generally, during dry etching, the conductive film 7 to be etched is charged positively or negatively by ion bombardment.

FIG. 2(b) shows a case where the film is negatively charged. In this case, the film to be etched 7, which becomes the second layer wiring, and the gate electrodes 5a and 5b of the p- and n-channel transistors are electrically connected at the contact 8. Since the gate electrode 5 is electrically conductive, the gate electrode 5
A and 5b are also negatively charged like the film to be etched 7. At this time, since the substrate lO is grounded, in the n-channel transistor part, the n'' region 4 and the p-eI region 1 which is the substrate part
A forward electric field is applied to the junction with 0, and electrons are transferred from the second layer wiring 7 to the contact 12. It flows to the p- region IO via the n'' region 4. Therefore, the p-eJI region 10 and the gate electrode 5b have almost the same potential, and no high electric field is applied between them.

[Problem to be solved by the invention]

However, in the p-channel transistor section, since an electric field is applied in the opposite direction to the junction between the pJI region 3 and the n-region 2, which is the substrate section, the electrons in the film to be etched 7 are transferred between the p'' region 3 and the n-6 region.
It cannot flow to n-6, 1 area 2 via the junction of 1 area 2. Therefore, a potential difference is generated between n- region 2 and gate electrode 5a, and a high electric field is applied. If this electric field exceeds the breakdown voltage limit of the gate silicon oxide film 6a between the two, the gate silicon oxide film 6a will be damaged by electrostatic discharge.

When the film to be etched 7 is positively charged, the gate electrode 5b and p-9 of the n-channel transistor section are similarly charged.
A high electric field is applied between regions 10 and 10, and the gate silicon oxide film 6
b leads to electrostatic damage.

In order to improve the accuracy of dry etching in microfabrication, it is necessary to improve the etching anisotropy and ion density, and as a result, ion bombardment on the film to be etched tends to increase. In addition, as semiconductor devices such as ICs and LSIs become finer, gate silicon oxide films are becoming smaller and smaller.
It is expected that as the film becomes thinner and thinner, the withstand voltage limit will decrease. Therefore, it is believed that the electrostatic breakdown phenomenon of the gate silicon oxide film that occurs during dry etching will become an increasingly serious problem in the future.

The present invention has been made in view of the above points, and its purpose is to prevent the charging phenomenon of the processed film due to the impact of charged particles caused by ions, etc. during dry etching processing, etc. An object of the present invention is to provide a method for manufacturing a semiconductor device in which a gate dielectric film does not suffer from electrostatic breakdown.

[Means to solve the problem]

In order to distantly achieve such an object, the present invention aims at forming a conductive processed film having electrical contact with a gate electrode and a region having the same conductivity type as the substrate portion facing the gate electrode during the manufacturing process. An electrical contact is formed between them.

[Effect]

In the method for manufacturing a semiconductor device according to the present invention, when a film to be processed is charged by charged particles such as ions and electrons during dry etching treatment, the gate electrode and the substrate portion facing the gate electrode have approximately the same potential, A high electric field is not generated between the two, and electrostatic damage to the gate dielectric film is avoided.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

Figures 1(a) and (b) show 0MO5 in the manufacturing process.
FIG. 2 is a plan view and a cross-sectional view showing a transistor structure of FIG.

FIG. 1(a) is a plan view showing a state in which the pattern formation of the second layer wiring is completed. Figure 1('b) is similar to Figure 1(a).
) is a cross-sectional view taken along line I-11 of FIG.

In FIG. 1, numerals 1 to 14 are the same as in FIG. 2,
Reference numeral 15a indicates a contact between the film to be etched 7 and the n-region 2, that is, a region of the same conductivity type as the substrate portion facing the gate electrode 5a. 10, that is, contact with a region of the same conductivity type as the substrate portion facing the gate electrode 5b.

FIG. 1 shows a case where the conductive film to be etched 7 is negatively charged. In this case, as in FIG. Gate electrode 5a.

Since the electrode 5b is electrically conductive through the contact 8, the gate electrodes 5a and 5b are also negatively charged like the film to be etched 7. At this time, in the p-channel transistor section, as in the conventional example, an electric field is applied in the opposite direction to the junction between the p'' region 3 and the n-? However, since a forward electric field will be applied to the junction between the n-SR region 2 and the p-region 10, the electrons in the film to be processed 7 will be transferred between the film to be processed 7 and the n-95 region 2.
It enters the n- region 2 from the contact 15a with the p-eI region 10 through the junction between the n- region 2 and the p region 10. Therefore, the 1,91 region 2 and the gate electrode 5a have almost the same potential, and no high electric field is applied between them. Therefore, electrostatic damage to the gate silicon oxide film 6a between the two can be avoided. At this time, in the n-channel transistor section, as in the conventional example, electrons in the film to be processed 7 are transferred to the contact 1.
2 to n″ area 4, n″ area 4 and p-91 area IO
flows to the p-81 region 10 through the junction of p-eM
The region 10 and the gate electrode 5b are at approximately the same potential, and no electrostatic damage occurs to the gate silicon oxide film 6b.

Further, when the film to be etched 7 is positively charged, the n9 region 4 of the n-channel transistor portion and the p-
Since an electric field in the opposite direction is applied to the junction in region 10,
Electrons in the film to be etched 7 do not flow out from the contact 12 between the film to be etched 7 and the n'' head region 4, but the electrons in the film to be etched 7 do not flow out from the contact 15b between the film to be etched 7 and the p-eM region 10.
The electrons flow out into the pi region 10, and the p-ViI region 10 and the gate electrode 5b have almost the same potential, and the gate silicon oxide film 6b between them is spared from electrostatic damage.

As described above, the conductive etched lI is provided in each of the p-channel transistor section and the n-channel transistor section 5.
! 7 and the same conductive shadow region as the substrate portion facing the gate electrode, the gate dielectric in the p-channel and n-channel transistors is It is possible to prevent static destruction of body membranes. Note that in the contacts 15a and 15b, since the film 7 to be etched has disappeared when the etching of the film 7 to be etched is completed, the contact does not function as a contact, and in the subsequent steps, the shape remains as a mere hole in the interlayer insulating film 1. This does not affect the performance of the semiconductor device in any way.

Furthermore, in the above embodiment, the case of a CMO3I-transistor structure in which an n-channel transistor and a p-channel transistor are combined is shown, but of course, it can also be applied to a structure of an nMO3) transistor or a pMOS transistor with only an n-channel or a P-channel. A similar effect can be obtained.

Furthermore, in the above embodiment, the conductive film to be processed is in direct contact with a region of the same conductivity type as the substrate portion facing the gate electrode. For the n'' region, 1)-TlI region, a p'' region is formed in the contact portion in advance, and then the film to be processed is formed as a bottom layer.
Contacts may also be formed. This reduces the contact resistance between the two in the contact portion, increasing the effect.

〔Effect of the invention〕

As explained above, in the present invention, during the manufacturing process, an electrical contact is made between a conductive processed film having an electrical contact with a gate electrode and a region of the same conductivity type as the substrate portion facing the gate electrode. By forming , the charged particles in the film to be processed can flow out of the substrate, so there is no need to add any additional manufacturing process or extend the processing time, just by adding a small mask pattern. Moreover, it has the effect of preventing electrostatic breakdown of the gate dielectric film against charging of the processed film due to the impact of charged particles during dry etching processing, etc., without affecting the performance of the semiconductor device in any way.

[Brief explanation of drawings]

FIGS. 1(al) and (b) show a CMO in the manufacturing process for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention.
A plan view and a cross-sectional view showing a type 3 O3 transistor structure, 2nd
Figures (a) and (b) show CMO3 type O in the conventional manufacturing process.
FIG. 3 is a plan view and a cross-sectional view showing a three-register structure. l...isolated silicon oxide film, 2...n-91 region,
3... p'' area, 4... n'' area 5a, 5b...
1st layer wiring, 5a, 5b... Gate silicon oxide film, 7... Film to be etched, 8... Contact, 9...
...Silicon oxide film, 10...p-type silicon substrate, 1
1,12゜15a, 15b...Contact, 13...
-Resist pattern, 14...Ion injection.

Claims (1)

[Claims] In the manufacturing process, an electrical contact is formed between a conductive processed film having electrical contact with the gate electrode and a region having the same conductivity type as the substrate portion facing the gate electrode. A method for manufacturing a semiconductor device.