JPH0371625A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the breakdown of a gate insulating film for restraining the increase in the connection resistance to a polySi gate by a method wherein, in the two time ion-implantation processes to form S/D regions of two kind MOSFETs, resist masks are provided over a gate connecting electrode formation part of a polySi layer for ther implantation. CONSTITUTION:At least in one process out of an ion-implantation process of the first conductivity type impurity masking a part of transistor formation region and another ion-implantation process of the second conductivity type impurity masking a part of the transistor formation region, the part connecting to a wiring metallic layer of a polySi gate electrode 3 of a transistor is processed not to be ion-implanted. In order to avoid the ion-implantation in a gate, contact formation part 4 of a polySi layer, the part 4 is covered with e.g. resist 7a, 7b. Through these procedures, if the ion-implantation process is not performed at least in one process, the resistance will not be increased by compensation; whereas even if the resistance is increased in such a fine region as the contact formation part 4, the breakdown strength of a gate oxide film will not be increased to the significant extent.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an ion implantation process in the formation of a CMO3 type ICO, which avoids destruction of the gate insulating film during the ion implantation process and suppresses an increase in connection resistance to the polySt gate. In order to achieve this, in the two ion implantations to form the S/D regions of the two types of MOSFETs, in addition to the minimum required resist mask, a resist mask was also applied to the gate connection electrode forming part of the poly-Si layer. The configuration is such that implantation is performed with a mask provided.

[Industrial application field]

The present invention relates to the formation of MO3 type integrated circuits, and in particular to an ion implantation process that does not involve dielectric breakdown of the gate insulating film.

2. Description of the Related Art As semiconductor integrated circuits become more highly integrated, the elements that make up the circuits become smaller. The basic method for miniaturizing active elements such as transistors is to reduce all dimensions of the element at a fixed ratio, which is called the scaling law.

Insulated gate field effect transistor (hereinafter referred to as MOS F)
When applying the scale law to ET), not only the dimensions shown in a plane are changed, but also the dimensions shown in a vertical section are changed as well, so the thickness of the gate insulating film is also 200 mm.
It has become as thin as a human being, creating a situation where there is little margin for dielectric strength.

Nowadays, advances in process technology have improved the characteristics of gate insulating films, and dielectric breakdown almost no longer occurs during normal operation. The problem of destruction of the gate insulating film has arisen as the film becomes thinner. This type of failure often occurs over time during use even if the product is normal in the initial operation test, making it difficult to distinguish between good and defective products.

[Conventional technology]

Among MO3 type ICs, both n-channel and p-channel M
In the manufacture of CMO3 type O3 with OSFET, poly5
After the gate electrode of the iFJ is formed, the S/D region of the transistor is formed by two ion implantations. This ion implantation step is shown in FIGS. 3(a) and 3(b), and will be described with reference to the same drawings.

The drawing is a schematic diagram showing a vertical cross section of the Si substrate l,
The substrate is p-type, with an n-type well 2 and a poly-Si gate electrode 3.
has already been formed, and ion implantation is performed thereon as shown in the figure to form a MOSFET. 5 is a field oxide film.

First, the n-type well region is masked with a photoresist 7 (hereinafter referred to as resist), and As is ion-implanted at an acceleration voltage of 60 KeV and a dose of about IXIO cm-.The gate electrode and field oxide film are masked. Then,
An S/D SI region 6a of "n" is formed. This state is shown in FIG. In order to avoid redundancy, a description of this type of heat treatment process will be omitted below.

Next, as shown in (1) of the same figure, the formed n-channel transistor region is masked with a resist 7 and ions of, for example, B4 are implanted.
Region 6b is formed to create a p-channel transistor. The conditions for this implantation are, for example, an acceleration voltage of about 12 KeV and a dose of about IXIOlscm-''.
In place of B' injection, BF+ or BF,'' may be injected, but the injection conditions in that case are also set to the above level in terms of Bo.

In these ion implantation processes, high-concentration ion implantation is performed, but the negative effects of static electricity during this process pose a problem. That is, when a high dielectric constant film such as a resist is irradiated with an ion beam, charge accumulation (charge-up) occurs, and the accumulated charge is discharged toward a nearby conductor.

If the conductor receiving the discharge is the polySt gate electrode or its extension, a high electric field will be applied to the gate insulating film, causing dielectric breakdown.

In order to suppress the occurrence of such a situation, efforts are being made to reduce the area covered by the resist as much as possible to reduce the amount of charge accumulated on the resist film.

In the example shown in FIG. 3, ion implantation is performed while covering only the region where an element of the opposite conductivity type is to be formed with a resist film.

[Problem to be solved by the invention]

When ion implantation is performed while masking only the element region of the opposite conductivity type as in the process shown in FIG.
Both n-type and p-type ions will be implanted.

FIG. 2 is a plan view illustrating the element shape of CMO3, and as shown in the figure, the poly-Si gate electrode 3 is extended outside the element area, and the contact forming portion 4 provided in the extended portion is Connected to metal wiring.

Since the doses of the two ion implantations in the above process are similar, both types of impurities compensate each other within the polySt, increasing its specific resistance and increasing the connection resistance to the metal wiring. As a result, the characteristics of the IC become unstable, resulting in the production of defective products.

An object of the present invention is to provide a method for manufacturing a CMO3 type O3 without increasing the contact resistance of poly-Si due to ion implantation for forming two types of MOSFETs on the same substrate.

[Means to solve the problem]

In order to achieve the above object, in the method for manufacturing a semiconductor device of the present invention, during the step of forming an insulated gate field effect transistor on a semiconductor substrate, a part of the transistor formation region is masked to form a first conductivity type field effect transistor. In at least one of the step of ion-implanting an impurity or the step of ion-implanting a second conductivity type impurity while masking another part of the transistor formation region, the wiring metal of the poly-Si gate electrode of the transistor is The portions connected to the layers are treated so that the ion implantation is not performed.

[For production]

In order to prevent ion implantation into the gate contact forming portion of the poly-Si layer, for example, this portion is coated with a resist. Unless at least one of the ion implantations is performed, the resistance will not increase due to compensation. Further, even if the resist area increases only in a minute region such as a contact forming portion, the dielectric breakdown of the gate oxide film does not significantly increase.

〔Example〕

FIG. 1 is a diagram schematically showing the process of an embodiment of the present invention, and FIGS. FIG. 3 is a cross-sectional view showing the second stage of the process. Hereinafter, the steps of the embodiment will be described with reference to these drawings. Note that the meanings of the reference numerals of each part in FIG. 1 are the same as in FIG. 3 unless otherwise specified.

The steps shown in FIGS. 3(a) and 3(b) correspond to the steps shown in FIG. 3(a) showing the prior art. An n-type well 2 and a field oxide film 5 are prepared on a p-type St substrate 1, and a poly-Si
The layer is patterned to create a gate electrode 3 and contact formations 4 for the electrode.

In this process as well, As'' ion implantation is performed with the n-type well region masked with the resist 7a, but the difference from the conventional technique is that in the embodiment, in addition to the well region, the contact formation portion is also masked with the resist 7a. This is what is being done.

Similarly, in the subsequent step shown in FIG.
is masked with a resist 7b, and ion implantation of B'' is performed.The doses in the above two ion implantations are the same as in the prior art.

Impurity doping for the poly-Si gate electrode is usually done by adding impurity raw materials to the raw material gas when forming the poly-Si layer by the CVD method. Although it has been
Since it is only necessary to prevent the implantation of ions of a conductivity type opposite to that of the originally contained impurities, a mask may be provided for the contact forming portion only in the corresponding ion implantation step.

〔Effect of the invention〕

When various types of ions are implanted into the poly-Si layer as in the conventional technology, for example, the average contact resistance value of a 2 μm diameter connection electrode is about 200Ω, but in the present invention, it is suppressed to about 50Ω. .

As described above, according to the present invention, it is possible to suppress an increase in the connection resistance between the poly-Si layer and the metal wiring, thereby reducing the failure rate of CMO3 type O3.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the process of the embodiment, Fig. 2 is a plan view illustrating a CMO3 element, and Fig. 3 is a schematic diagram showing the process of the conventional technology, in which 1 is a Si substrate. , 2 is an n-type well, 3 is a gate electrode, 4 is a contact formation part for the gate electrode, 5 is a field oxide film, 6.6a, 6b are S/D Off regions, 7, 7a,
7b is a resist. Schematic diagram illustrating the process of an example Diagram illustrating the shape of a CMOS element Schematic diagram illustrating the process of the prior art

Claims (1)

[Claims] In the step of forming an insulated gate field effect transistor on a semiconductor substrate, a step of ion-implanting impurities of a first conductivity type while masking a part of the transistor formation region or the transistor formation region In at least one of the steps of ion-implanting a second conductivity type impurity while masking the other part of the transistor, the ion implantation is performed on a portion of the poly-Si gate electrode of the transistor connected to the wiring metal layer. A method for manufacturing a semiconductor device, characterized in that: