JP2001217321A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce decrease of a threshold voltage caused by short channel effect, deterioration of subthreshold characteristic, decrease of punch through withstanding voltage, etc., and can realize microstructure by having different threshold voltages in the same chip and constituting the entire device by using surface channel transistors, and a manufacturing method of a semiconductor device wherein manufacturing is enabled without needing an additional process and a mask. SOLUTION: In this semiconductor device, an N well diffusion layer 2 and a P well diffusion layer 3 which are arranged adjacently are disposed. A P gate PMOS transistor 100 having a P-type gate electrode 71 and an N gate PMOS transistor 101 having an N-type gate electrode 72 are formed in the same N well diffusion layer 2. A P gate NMOS transistor 200 having a P-type gate electrode 71 and an N gate NMOS transistor 201 having an N-type gate electrode 72 are formed in the same P well diffusion layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having different threshold voltages in the same chip and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, some LSI circuits have different threshold voltages in the same chip. In this type of LSI circuit, the threshold voltage is generally controlled by changing the substrate impurity concentration immediately below the gate electrode by ion implantation or the like using an additional mask.

Further, a technique of changing the threshold voltage by changing the thickness of the gate oxide film is also used.

Further, in order to lower the resistance of a gate electrode made of polycrystalline silicon, a two-layer gate formed by applying a metal (for example, tungsten or titanium to a silicide by sputtering and heat treatment) is applied to the polycrystalline silicon. For a semiconductor device constituting a gate electrode, the threshold voltage is changed by changing the relationship between the thickness of the polycrystalline silicon of the gate electrode and the thickness of the metal deposited on the surface of the polycrystalline silicon. Techniques such as controlling the voltage in a range defined by a change in the work function value have been used.

On the other hand, Japanese Unexamined Patent Publication No. Hei 8-213476 discloses that a part of an NMOS (or PMMO) is used in a semiconductor device using N and P type conductive polysilicon for an NMOS transistor and a gate electrode of a PMOS transistor, respectively.
S) A method for manufacturing a semiconductor device in which transistors having different threshold voltages are simultaneously manufactured by using a P-type (or N-type) gate for a transistor is disclosed.

[0006]

In each of the above-described conventional semiconductor devices and the method of manufacturing the same, an additional step or an additional mask is required in each case, so that the manufacturing time is increased and the manufacturing cost is increased. When the polarity of the gate electrode and the polarity of the substrate of the transistor are the same, the conventional transistor becomes a buried channel type because the channel voltage is lowered to lower the threshold voltage. There have been problems such as a decrease in threshold voltage due to the effect, (2) a deterioration in subthreshold characteristics, and (3) a decrease in punch-through-withstand voltage.

In the prior art disclosed in JP-A-8-213476, an N-gate NMOS transistor,
Since the P-gate PMOS transistor, the P-gate NMOS transistor, and the N-gate PMOS transistor are arranged adjacent to each other with the field oxide film interposed therebetween, a PMO having a P-type gate electrode and an N-type gate electrode is provided.
It is more difficult to miniaturize compared to a case where an S transistor and an NMOS transistor having a P-type gate electrode and an N-type gate electrode are arranged adjacent to each other. Further, since the ion implantation to the gate electrode and the ion implantation to the source / drain are performed in separate steps, the manufacturing time is lengthened accordingly and the manufacturing cost is increased.

An object of the present invention is to provide a semiconductor device having different threshold voltages in the same chip, all of which are made up of surface channel transistors, thereby lowering the threshold voltage due to the short channel effect, deteriorating the sub-threshold characteristic, and reducing punch-through characteristics. −
It is an object of the present invention to provide a semiconductor device capable of reducing a decrease in breakdown voltage and the like and achieving miniaturization.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing semiconductor devices having different threshold voltages in the same chip without requiring additional steps and masks. It is in.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
P-gate PMOS transistor having an N-well diffusion layer and a P-well diffusion layer disposed adjacent to each other and having a P-type gate electrode, and an N-gate PMOS having an N-type gate electrode
A transistor is formed in the same N-well diffusion layer,
A P-gate NMOS transistor having a P-type gate electrode and an N-gate NMOS transistor having an N-type gate electrode are formed in the same P-well diffusion layer.

The impurity concentration of the P-type gate electrode or the N-type gate electrode may be different for each transistor.

[0012] The transistor may have an LDD structure.

It is preferable that the width of the sidewall of the transistor is about twice as large as the amount of deviation from the gate electrode which occurs during an exposure process for forming a source and a drain.

According to a first method of manufacturing a semiconductor device of the present invention,
Forming an N-well diffusion layer and a P-well diffusion layer, and forming a gate electrode on the N-well diffusion layer and the P-well diffusion layer; and a source region and a drain of a PMOS transistor to be formed in the N-well diffusion layer. Simultaneously implanting a P-type impurity into a region and a gate electrode to be made P-type; a source region and a drain region of an NMOS transistor to be formed in the P-well diffusion layer; Simultaneously injecting N-type impurities into the electrodes.

According to a second method of manufacturing a semiconductor device of the present invention,
An N-well diffusion layer and a P-well diffusion layer are formed, and the N-well diffusion layer and the P-well diffusion layer are each doped with a polycrystalline silicon gate electrode having a low concentration of an N-type impurity and a low-concentration P-type impurity. Forming a polycrystalline silicon gate electrode, and forming a PMOS to be formed in the N-well diffusion layer.
Simultaneously implanting a P-type impurity into a source region and a drain region of the transistor and a gate electrode to be made highly P-type; a source region and an NMOS transistor to be formed in the P-well diffusion layer; And a step of simultaneously implanting an N-type impurity into a drain region and a gate electrode to be made highly-N-type.

It is preferable that the implantation of the impurity be separately performed using a mask.

The mask has an opening inside the gate electrode when impurities are implanted into the gate electrode, and an opening outside the gate electrode when impurities are not implanted into the gate electrode. The gate electrode is formed inside and outside the gate electrode.
It is preferable to be located at a position from the edge of the gate electrode to the amount of deviation from the gate electrode which occurs during the exposure process for forming the source and drain.

According to the semiconductor device of the present invention, the P-gate PMOS transistor formed on the N-well diffusion layer includes:
Since the work function difference between the P-type gate electrode and the N-well diffusion layer is large, the threshold voltage is lowered and the N-gate PMO
Since the work function difference between the N-type gate electrode and the N-well diffusion layer is small in the S transistor, the threshold voltage increases in the negative direction, and the P-gate NMOS transistor is
Since the work function difference between the gate electrode and the P-well diffusion layer is small, the threshold voltage increases, and the N-gate NMOS
The threshold voltage of the transistor is low because the work function difference between the N-type gate electrode and the P-well diffusion layer is large. Further, the threshold voltage can be further increased by changing the impurity concentration of the gate electrode.

As described above, by changing the polarity or impurity concentration of the gate electrode, different threshold voltages can be provided in the same chip.

According to the method of manufacturing a semiconductor device of the present invention,
By simultaneously performing ion implantation into the gate electrode and ion implantation into the source and drain without requiring an additional step and mask, a semiconductor device having different threshold voltages in the same chip can be manufactured. .

[0021]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, a semiconductor device according to an embodiment of the present invention includes a P-type silicon substrate 1 and N-well diffusion layers 2 and P formed on the P-type silicon substrate 1 and arranged adjacent to each other. A well diffusion layer 3, a P-gate PMOS transistor 100 and an N-gate PMOS transistor 101 formed in the N-well diffusion layer 2,
P-gate NMOS transistor 200 and N-gate NMOS transistor 201 formed in P-well diffusion layer 3
And

That is, in each transistor of the present invention,
For the same NMOS transistor, a P-gate NMOS transistor 200 having a P-type gate electrode 71 and an N-gate NMOS transistor 201 having an N-type gate electrode 72
And a P-gate PMOS transistor 100 having a P-type gate electrode 71 and an N-type
It is composed of four types of N-gate PMOS transistors 101 having a gate electrode 72.

Each transistor is provided with a source diffusion layer 4, a drain diffusion layer 5, and a gate oxide film 6, respectively.

In this embodiment, the threshold voltage is 0.2
NMOS transistor and PMOS transistor of about 0.4 V (absolute value) and threshold voltage 1 V (absolute value)
Some NMOS and PMOS transistors are formed in the same chip. Note that the value of the threshold voltage is an example and is not limited to this.

FIGS. 2A and 2B simulate the substrate bias characteristics (substrate bias (V) -threshold voltage (V)) of each transistor of the semiconductor device according to the embodiment of the present invention. It is a graph which shows the result.

FIG. 2A shows the substrate bias characteristics of the NMOS transistor. Where ● is an N-gate NMOS
The substrate bias characteristics of the transistor 201 are shown.
4 shows a substrate bias characteristic of the gate NMOS transistor 200. As can be seen from FIG. 2A, the N-gate NMO
The P-gate NMOS transistor 200 is about 1 V higher than the S transistor 201 at a substrate bias of 0 V (threshold voltage).

FIG. 2B shows the substrate bias characteristics of the PMOS transistor. Where ● is a P-gate PMOS
The substrate bias characteristic of the transistor 100 is shown.
4 shows a substrate bias characteristic of the gate PMOS transistor 101. As can be seen from FIG. 2B, the P-gate PMO
The N-gate PMOS transistor 101 is about 1 V higher than the S transistor 100 at a substrate bias of 0 V (threshold voltage).

As described above, the NMOS transistor 20
0 and 201 and the PMOS transistors 100 and 101 have the same channel depth, but the substrate bias characteristics are different between the NMOS transistors 200 and 201 and the PMOS transistors 100 and 101.

Here, the result of the simulation shown in FIG. 2 will be briefly described. The threshold voltage of a MOS transistor is expressed by the following equation. VT can be controlled by changing any of the parameters. In the present invention, different transistors are formed on the same chip by changing the work function φMS.

VT = φMS−Qss / Co + 2φf − ((2ε
iεoqNsub (| 2φf | + Vsub) ^1/2 / Co) where φMS: work function between the gate electrode and the silicon substrate Qss: interface state density Co: gate capacity per unit area φf: Fermi potential εi: dielectric constant of the gate oxide film εo: dielectric constant in vacuum q: electric charge of electron Nsub: substrate impurity concentration Vsub: substrate bias voltage First, the PMOS transistor will be described. The threshold voltage of the P-gate PMOS transistor 100 formed on the N-well diffusion layer 2 is low because the work function difference between the P-type gate electrode 71 and the N-well diffusion layer 2 is large. However, the N well formed on the same N well diffusion layer 2
In the gate PMOS transistor 101, since the work function difference between the N-type gate electrode 72 and the N-well diffusion layer 2 is small, the threshold voltage increases in the negative direction. For this reason,
Generally, the N-gate PMOS transistor 101 is doped with an impurity of the conductivity type opposite to that of the substrate in the channel region in order to lower the absolute value of the threshold voltage. In this embodiment, since a surface channel type is required and a relatively high threshold is required due to the characteristics of the circuit, it is used without performing channel doping.

Similarly, in the case of the NMOS transistor, the P-gate NMOS transistor 200 has a small work function difference between the P-type gate electrode 71 and the P-well diffusion layer 3 and therefore has a high threshold voltage, The threshold voltage of the NMOS transistor 201 is low because the work function difference between the N-type gate electrode 72 and the P-well diffusion layer 3 is large.

In other words, the N-gate NMOS transistor 201 or the P-gate PMOS transistor 100 having a large work function difference by utilizing the work function difference is
P-type NMOS transistor 200 or N-gate PMOS transistor having a threshold value of about 0.2 to 0.4 V and having a small work function difference.
Since the transistor 101 has the same substrate concentration as the N-gate NMOS transistor 201 or the P-gate PMOS transistor 100, the threshold voltage of the transistor 101 is 1 in absolute value.
It becomes a surface channel type transistor of about V.

Here, the necessity of the transistor being a surface channel type is described below. The transistor of each channel is N
By providing the P-type and P-type gate electrodes, the threshold voltage is changed by the difference in work function φms between the gate electrode and the silicon substrate without changing the substrate impurity concentration Nsub. Therefore, since all the transistors are of the surface channel type, it is possible to reduce the drawbacks of the buried channel type such as a decrease in threshold voltage due to a short channel effect, a deterioration in subthreshold characteristics, a decrease in punch-through breakdown voltage, and the like.

FIG. 2C simulates the dependence of the gate electrode concentration on the threshold voltage of the NMOS transistor.
6 is a graph showing the result of the operation. Here, ● represents the gate electrode concentration of the N-gate NMOS transistor 201, and Δ represents the gate electrode concentration of the P-gate NMOS transistor 200. As can be seen from FIG. 2 (C), even if the substrate concentration (N-well and P-well concentrations) is constant,
It can be seen that the threshold voltage can be controlled by changing the impurity concentration of the gate electrode.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG.

First, an N-well diffusion layer 2 and a P-well diffusion layer 3 are formed on a P-type silicon substrate 1 so as to be adjacent to each other. Then, polycrystalline silicon is deposited via the gate oxide film 6, and a gate electrode is formed by an etching technique (see FIG. 3A).

Next, except for the source for forming the PMOS transistor and the drain and the gate electrode to be made P-type, the resist 8 is masked with a resist 8 using a lithography technique, and Hucaboron (BF ₂ ) as a P-type impurity is formed. Ions are implanted at an energy of 30 KeV and a dose of 3.0E15 cm- ² (see FIG. 3B).

Next, the resist 8 as a mask material is peeled off (see FIG. 3C).

Next, except for the source and the drain and the gate electrode to be made N-type to form an NMOS transistor, the lithography technique is used to similarly mask the resist 8 using a lithography technique to remove arsenic (As) as an N-type impurity. Energy-50
Ion implantation is performed with KeV and a dose of 1.5E15 cm ⁻² (see FIG. 3D).

Next, the resist 8 as a mask material is peeled off (see FIG. 3E). Thereby, the semiconductor device according to the embodiment of the present invention is completed.

FIGS. 4A and 4B are explanatory diagrams for explaining the arrangement of masks used in the method of manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 4 (A)
FIG. 2 is a schematic cross-sectional view when the mask 9 used for forming the source and the drain and the P-type silicon substrate 1 are aligned. Although it depends on the type of resist (positive type or negative type), in the present embodiment, it is assumed that an impurity is introduced into a place where no mask exists, the gate width dimension L1 is 0.35 μm, and the MOS transistor LDD (lightly) for relaxing the electric field near the drain of
Doped Drain) devices,
The width of the side wall 10 of the transistor is 0.0, which is twice as large as the shift amount L2 (about 0.04 μm) from the gate electrode generated during the exposure process for forming the source and drain.
8 to 0.1 μm is provided. Note that sidewall 1
No. 0 is formed by depositing polysilicon on the entire surface of the wafer, patterning, processing a gate electrode by etching, depositing an oxide film on the entire surface, and performing an etch bag. In addition, the shift amount 0.04 μm is generally the maximum value of the shift amount in a device having a gate size rule of 0.35 μm.

In the source and drain forming step, the mark formed by the gate electrode 70 is registered (not shown), and the standard of the amount of displacement at that time is 0.04 μm. For this reason, the mask dimension L3 for masking the gate electrode 70 is made up of the gate electrode 0.35 um + the shift amount 0.04 um × 2 = 0.43 um. Also gate electrode 7
No impurity is introduced into the source 0 and the impurity is introduced only into the source and the drain.

FIG. 4B is a schematic cross-sectional view when the mask 9 used for implanting impurities only into the gate electrode 70 and the P-type silicon substrate 1 are aligned. Also in this case, the mask 9 is 0.35 μm of the gate electrode 70 + 0.04 μm × 2 = 0.43 μm with respect to the gate electrode 70.
With the opening having the size L4, an impurity is introduced only into the gate electrode 70, and no impurity is introduced into the source and the drain. In each case, it is understood that the side wall 10 having a width twice as large as the shift amount plays an important role.

Thereafter, the impurity is uniformly diffused into the gate electrode 70 by the annealing after the impurity is introduced into the gate electrode 70.

However, since an exposure apparatus used for actual LSI manufacture uses a reduction projection exposure apparatus, the mask is 5 mm.
It becomes about 10 times larger.

Next, a method for changing the concentration of the gate electrode will be described. For example, if the gate electrode of N-type polycrystalline silicon doped at a low concentration is masked so that impurities for forming a source and a drain do not enter, a low concentration N-gate NMOS transistor or a low concentration N-type polycrystalline silicon is formed. Concentration N gate PM
An OS transistor can be formed. Similarly, if P-type polycrystalline silicon doped at a low concentration is used as a gate electrode, a low-concentration P-gate NMOS transistor or a low-concentration P-gate PMOS transistor can be formed. Also,
A P-type impurity is implanted into the gate electrode to be made highly P-type, and an N-type impurity is simultaneously implanted into the gate electrode to be made highly N-type.

As described above, according to another method of manufacturing a semiconductor device of the present invention, a high-concentration N-gate and a low-concentration N-gate transistor can be used without requiring a process and an additional mask. The P-gate and P-gate transistors can be configured as a surface channel type in the NMOS transistor and the PMOS transistor.

As described above, since the polarity or concentration of the gate electrode is changed together with the process of forming the source and drain regions of the transistor, there is no additional process even in the same chip, and the low threshold voltage is not required. A surface channel transistor which can obtain a value voltage and a high threshold voltage can be formed.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the technical matters described in the claims. For example, boron or the like may be used as the P-type impurity, or phosphorus or the like may be used as the N-type impurity. Further, as disclosed in JP-A-8-213476, an N-gate NMOS transistor, a P-gate PMOS transistor, and a P-gate NMOS are manufactured by using the method of manufacturing a semiconductor device of the present invention.
It is also possible to manufacture a semiconductor device arranged adjacent to a transistor and an N-gate PMOS transistor in this order.

[0050]

According to the semiconductor device of the present invention, an NMOS transistor and a PMOS transistor having a low threshold voltage of, for example, about 0.2 to 0.4 V and a high threshold voltage of about 1 V are provided in the same chip. For example, an NMOS transistor having different gate electrodes and a PM
Since the OS transistor can be configured as a surface channel transistor, a reduction in threshold voltage due to a short channel effect, a deterioration in subthreshold characteristics, a reduction in punch-through withstand voltage, and the like can be reduced.

By changing the impurity concentration of the gate electrode, more threshold voltages can be obtained.

Further, since a PMOS transistor having a P-type gate electrode and an N-type gate electrode and an NMOS transistor having a P-type gate electrode and an N-type gate electrode are arranged adjacent to each other, the P-gate PMOS transistor and the N-type Between gate PMOS transistor and P gate NM
No field oxide film (element isolation region) is required between the OS transistor and the N-gate NMOS transistor.
The miniaturization can be achieved as compared with the semiconductor device disclosed in JP-A-8-213476.

According to the method of manufacturing a semiconductor device of the present invention,
By simultaneously performing ion implantation into the gate electrode and ion implantation into the source and drain without requiring an additional step and mask, a semiconductor device having different threshold voltages in the same chip can be manufactured. Therefore, it is possible to reduce the manufacturing time and the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A and 2B simulate the substrate bias characteristics (substrate bias (V) -threshold voltage (V)) of each transistor of the semiconductor device according to the embodiment of the present invention; It is a graph which shows a result, (C) is
9 is a graph showing the result of simulating the dependence of the gate electrode concentration on the threshold voltage of an NMOS transistor.

FIG. 3 is a sectional view illustrating a method of manufacturing the semiconductor device according to the embodiment of the present invention in the order of steps.

FIGS. 4A and 4B are explanatory diagrams for explaining an arrangement of a mask used in a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIGS.

[Explanation of symbols]

 1: P-type silicon substrate 2: N-well diffusion layer 3: P-well diffusion layer 4: source diffusion layer 5: drain diffusion layer 6: gate oxide film 70: gate electrode 71: P-type gate Electrode 72: N-type gate electrode 8: Resist 9: Mask 10: Side wall 100: P-gate PMOS transistor 101: N-gate PMOS transistor 200: P-gate NMOS transistor 201: N-gate NMOS transistor

Claims (8)

[Claims] An N-well diffusion layer and a P-well are disposed adjacent to each other.
A P-gate PMOS transistor having a P-type gate electrode and an N-gate PMOS transistor having an N-type gate electrode are formed in the same N-well diffusion layer, and a P-type PMOS transistor having a P-type gate electrode is provided. A semiconductor device, wherein a gate NMOS transistor and an N-gate NMOS transistor having an N-type gate electrode are formed in the same P-well diffusion layer. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the P-type gate electrode or the N-type gate electrode differs between the transistors. 3. The semiconductor device according to claim 1, wherein said transistor has an LDD structure. 4. The method according to claim 1, wherein the width of the side wall of the transistor is about twice as large as the amount of deviation from a gate electrode generated during an exposure process for forming a source and a drain. Item 4. The semiconductor device according to any one of Items 1 to 3. 5. A step of forming an N-well diffusion layer and a P-well diffusion layer, and forming a gate electrode on the N-well diffusion layer and the P-well diffusion layer; Simultaneously injecting a P-type impurity into a source region and a drain region and a gate electrode to be P-type; a source region and a drain region of an NMOS transistor to be formed in the P-well diffusion layer; Simultaneously implanting an N-type impurity into a gate electrode to be formed. 6. An N-well diffusion layer and a P-well diffusion layer are formed, and a polycrystalline silicon gate electrode in which a low-concentration N-type impurity is introduced into the N-well diffusion layer and the P-well diffusion layer. Forming a polycrystalline silicon gate electrode into which a p-type impurity has been introduced; a source region and a drain region of a PMOS transistor to be formed in the N-well diffusion layer; and a gate electrode to be made highly p-type. Simultaneously implanting a P-type impurity into the source and drain regions of the NMOS transistor to be formed in the P-well diffusion layer, and simultaneously implanting an N-type impurity into the gate electrode to be made highly N-type. A method of manufacturing a semiconductor device, comprising: 7. The method for manufacturing a semiconductor device according to claim 5, wherein the implantation of the impurities is performed separately using a mask. 8. The mask has an opening inside the gate electrode when impurities are implanted into the gate electrode, and an opening outside the gate electrode when impurities are not implanted into the gate electrode. And the inside and outside of the gate electrode are gated.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is located at a position corresponding to a shift amount from a gate electrode generated during an exposure step of forming a source and a drain from an edge of the gate electrode.