KR100204425B1 - Electrostatic discharge semiconductor device and manufacturing thereof - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a static discharge semiconductor device and a method of manufacturing the same, which can prevent accumulation of charge by plasma during wiring formation by using a separate conductive film pattern having a polarity opposite to that of an electrostatic discharge impurity region. The electrostatic discharge semiconductor device according to the present invention includes a first conductive semiconductor substrate; A field oxide film formed on the substrate; A transistor having a gate insulating film formed on a substrate on one side of the field oxide film, a gate, and a second conductive source / drain region formed on the substrate on both sides of the gate; A first conductivity type electrostatic discharge impurity region formed on the substrate on the other side of the field oxide film; First and second insulating layers formed on the entire surface of the substrate and having contact holes formed on the gate and the impurity region; A second conductive electrostatic discharge conductive film pattern for electrostatic discharge interposed between the first and second insulating films and formed on a portion of the field oxide film and the impurity region; And first and second wiring layers contacted with the gate and the impurity region through the contact hole.

Description

Electrostatic Discharge Semiconductor Device and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a static discharge semiconductor device capable of preventing the accumulation of static charges by plasma and a method for manufacturing the same.

Recently, as the manufacturing technology of semiconductor devices is improved, high integration and high speed are rapidly progressing. Accordingly, studies on wiring technologies that can freely design wiring and allow setting of wiring resistance and current capacity, etc., are being actively conducted.

As a general wiring forming method, a method of patterning a wiring by dry etching using plasma by a combination of halogen gas such as Cl 2, BCl ₃ , SF ₆ , and HBr using a predetermined photoresist pattern as an etching mask is mainly used. However, electrostatic charges continue to accumulate due to the electrostatic charge generated by the plasma, which in turn stresses the gate oxide film under the gate electrode connected to the wiring, thereby deteriorating the characteristics of the gate oxide film and improving reliability of the device. Lowers.

Therefore, a separate discharge device must be provided for discharging the above-mentioned static charge.

1 is a cross-sectional view showing a static discharge semiconductor device.

As shown in FIG. 1, the conventional electrostatic discharge semiconductor device includes the first conductive semiconductor substrate 1, the field oxide films 2a, 2b, 2c formed on the substrate 1, and the field oxide film ( 2b) the gate oxide film 3 and the gate 4 formed on the substrate on one side, and the second conductive source / drain regions 5 and 6 and the field oxide film formed on the substrate 1 on both sides of the gate 4 ( 2b) an insulating film 8 having a first conductivity type discharge type electrostatic discharge impurity region 7 formed on the substrate 1 on the other side, and a contact hole formed on the gate 4 and the impurity region 7. ) And first and second wirings 9a and 9b contacting the gate 4 and the impurity region 7 through the contact hole.

That is, as the interconnection of the impurity region 7 and the wiring is contacted, the static charge by dry etching by the plasma is discharged to the impurity region 7 at the time of formation of the wiring, so that accumulation of the static charge can be prevented.

However, the above-described conventional electrostatic discharge semiconductor device has the following problems depending on the polarity of the electrostatic charge.

That is, when the first conductivity type is n type, when negative charge occurs during dry etching by plasma for wiring formation, the negative charge is discharged to the substrate 1 through the second wiring 9b and the impurity region 7, When positive charges are generated, charges induced in the second wiring 9b are accumulated without being discharged. In contrast, when the first conductivity type is p-type, positive charges are discharged and negative charges are accumulated. As a result, a strong electric field is formed by the accumulated electrostatic charge, which stresses the gate oxide film 3, resulting in lowering the reliability of the device.

Accordingly, the present invention was created in view of the above-described problems, and an electrostatic charge capable of preventing charge accumulation by plasma during wiring formation by using a separate conductive film pattern having a polarity opposite to that of an electrostatic charge impurity region. An object thereof is to provide a low discharge semiconductor device and a method of manufacturing the same.

1 is a cross-sectional view showing a conventional electrostatic discharge semiconductor device.

2A to 2D are cross-sectional views illustrating a method of manufacturing a static discharge semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: first conductive semiconductor substrate 12: field oxide film

13: gate oxide film 14: gate

15/16: 2nd conductivity type source / drain region

100: transistor 17: first conductivity type electrostatic discharge impurity region

18: first oxide film 19: second conductivity type conductive film pattern

20: second oxide film 21: contact hole

22: wiring layer

Electrostatic discharge semiconductor device according to the present invention for achieving the above object is a first conductive semiconductor substrate; A field oxide film formed on the substrate; A transistor having a gate insulating film, a gate formed on the substrate on one side of the field oxide film, and a second conductive source / drain region formed on the substrate on both sides of the gate; A first conductivity type electrostatic discharge impurity region formed on a substrate on the other side of the field oxide film; First and second insulating layers formed on an entire surface of the substrate and having contact holes formed on the gate and the impurity region; A second conductive electrostatic discharge conductive film pattern interposed between the first and second insulating films and formed on a portion of the field oxide film and the impurity region; And first and second wiring layers contacting the gate and the impurity region through the contact hole.

In addition, a method of manufacturing an electrostatic discharge semiconductor device according to the present invention for achieving the above object comprises the steps of forming a field oxide film on the first conductive semiconductor substrate; Forming a gate insulating film and a gate on the substrate on one side of the field oxide layer, and forming a transistor by forming second conductive source / drain regions on the substrate on both sides of the gate; Forming a first conductivity type electrostatic discharge impurity region on a substrate on the other side of the field oxide film; Forming a first insulating film on the entire surface of the substrate; Forming a second conductive electrostatic discharge conductive film pattern on the first insulating film except for the transistor region; Forming a second insulating layer on the conductive layer pattern and the first insulating layer; Forming a contact hole by exposing a predetermined portion of the gate and the impurity region; And forming first and second wiring layers contacting the gate and the impurity region through the contact hole.

The conductive layer may be a polysilicon layer or an amorphous silicon layer, and the conductive layer pattern may be exposed at both sides of the contact hole formed on the impurity region to be connected to the second wiring layer.

The first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.

According to the present invention having the above structure, the positive charge and the negative charge generated during the etching by the plasma during the formation of the wiring are discharged through the impurity regions for the electrostatic discharge and the conductive film patterns having different polarities, thereby accumulating charge. You can prevent it.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

FIG. 2D is a cross-sectional view showing a static discharge semiconductor device according to an embodiment of the present invention, wherein the static discharge semiconductor device according to the present invention includes a first conductive semiconductor substrate 11 and a field oxide film formed on the substrate 11. A gate insulating film 13 and a gate 14 formed on the substrate 11 on one side of the 12a, 12b and 12c and the field oxide film 12b, and a second formed on the substrate 11 on both sides of the gate 14. A transistor 100 having conductive source / drain regions 15 and 16, a first conductive type electrostatic discharge impurity region 17 formed on the substrate 11 on the other side of the field oxide film 12b, and a substrate Interposed between the first and second insulating films 18 and 20 and the first and second insulating films 18 and 20 formed on the entire surface and having contact holes formed on the gate 14 and the impurity region 17. The second conductive electrostatic discharge conductive film pattern 19 for electrostatic discharge formed on the field oxide films 12a, 12b, 12c and a part of the impurity region 17, and the cone It consists of the gate 14 and the impurity region 17, the first and second wiring layers (22a, 22b) contact and via holes.

Next, a method of manufacturing an electrostatic discharge semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2D.

First, as shown in FIG. 2A, field oxide films 12a, 12b, and 12c are formed on the first conductive semiconductor substrate 11 using LOCOS (LOCal Oxidation of Silicon) technology. Subsequently, the gate oxide film 13 and the gate 14 are formed on the substrate 11 on one side of the field oxide film 12b, and both sides of the gate 14 inject the second conductive impurity ions into the substrate 11. The second conductive source / drain regions 15 and 16 are formed to form transistors 100 of the device.

Thereafter, the first conductivity type impurity ions are implanted into the substrate 11 on the other side of the field oxide film 12b in which the transistor 100 is not formed to form the first conductivity type impurity region 17 for electrostatic discharge. Then, the first oxide film 18 composed of one of TEOS oxide film, BPSG film, or composite film is formed on the entire surface of the substrate for insulation and planarization.

As shown in FIG. 2B, a conductive film containing a second conductivity type impurity, such as a polysilicon film or an amorphous silicon film, is deposited on the first oxide film 18 to a thickness of about 1,000 to 3,000 kPa. The conductive film is patterned to expose the first oxide film 18 on the transistor 100 by photolithography and etching to form a second conductive electrostatic discharge conductive film pattern 19. That is, the conductive film pattern 19 is formed so as to overlap the field oxide films 12a, 12b, 12c and the impurity region 17.

As shown in FIG. 2C, on the structure of FIG. 2B, the second oxide film 20 is formed with a TEOS oxide film or a BPSG film to have a thickness of about 500 to 2,000 mW for electrical insulation with the conductive film pattern 19. The contact holes 21a and 21b are formed by exposing the gate 14 and the upper part of the impurity region 17 by photolithography and etching processes, respectively. At this time, the conductive film patterns 19 on both sides of the contact hole 21b on the impurity region 17 are exposed. That is, in the etching process for forming the contact holes 21a and 21b, first, the second oxide layer 20 is first etched to expose the upper portion of the conductive layer pattern 19, and then the second conductive layer pattern 19 is secondary. After etching to expose the first oxide film 18, the first oxide film 18 is third-etched to expose the gate 14 and the impurity region 17.

As shown in FIG. 2D, a metal layer is deposited on the structure of FIG. 2C, and patterned by photolithography and etching processes, through which the gate 14 and impurity regions 17 pass through respective contact holes 21a and 21b. First and second wirings 22a and 22b are formed in contact with each other.

According to the above embodiment, the positive charges and the negative charges generated during the etching by the plasma during the formation of the wiring are discharged through the electrostatic discharge impurity regions and the conductive film patterns having different polarities, thereby preventing charge accumulation. Can improve the reliability.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (21)

A first conductive semiconductor substrate; A field oxide film formed on the substrate; A transistor having a gate insulating film, a gate formed on the substrate on one side of the field oxide film, and a second conductive source / drain region formed on the substrate on both sides of the gate; A first conductive type electrostatic discharge impurity region formed on a substrate on the other side of the field oxide film; First and second insulating layers formed on an entire surface of the substrate and having contact holes formed on the gate and the impurity region; A second conductive electrostatic discharge conductive film pattern interposed between the first and second insulating films and formed on a portion of the field oxide film and the impurity region; And a first wiring line and a second wiring layer contacting the gate and the impurity region through the contact hole. The electrostatic discharge semiconductor device according to claim 1, wherein the conductive film pattern has a thickness of 1,000 to 3,000 kPa. The electrostatic discharge semiconductor device according to claim 2, wherein the conductive film is a polysilicon film. The electrostatic discharge semiconductor device according to claim 2, wherein the conductive film is an amorphous silicon film. The electrostatic discharge semiconductor device of claim 1, wherein the conductive layer pattern is exposed at both sides of a contact hole formed on the impurity region to be connected to the second wiring layer. The electrostatic discharge semiconductor device according to claim 1, wherein the first insulating film is a film selected from a TEOS film or a BPSG film or a composite film of a TEOS film and a BPSG film. The electrostatic discharge semiconductor device according to claim 1, wherein the second insulating film has a thickness of 500 to 2,000 kPa. 8. The device of claim 7, wherein the second insulating film is a TEOS film or a BPSG film selected film. The electrostatic discharge semiconductor device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. The electrostatic discharge semiconductor device according to claim 1, wherein the first conductivity type is P type and the second conductivity type is n type. Forming a field oxide film on the first conductive semiconductor substrate; Forming a gate insulating film and a gate on the substrate on one side of the field oxide layer, and forming a transistor by forming second conductive source / drain regions on the substrate on both sides of the gate; Forming a first conductivity type electrostatic discharge impurity region on a substrate on the other side of the field oxide film; Forming a first insulating film on the entire surface of the substrate; Forming a second conductive electrostatic discharge conductive film pattern on the first insulating film except for the transistor region; Forming a second insulating layer on the conductive layer pattern and the first insulating layer; Forming a contact hole by exposing a predetermined portion of the gate and the impurity region; And forming first and second wiring layers in contact with the gate and the impurity region through the contact hole. 12. The method of claim 11, wherein the first insulating film is a film selected from a TEOS film or a BPSG film or a composite film of a TEOS film and a BPSG film. 12. The method of claim 11, wherein the conductive film pattern is 1,000 to 3,000 kV. The method of manufacturing a static charge discharge semiconductor device according to claim 13, wherein the conductive film is a polysilicon film. The method of claim 13, wherein the conductive film is an amorphous silicon film. 12. The method of claim 11, wherein the second insulating film has a thickness of 500 to 2,000 kPa. 17. The method of claim 16, wherein the second insulating film is one selected from a TEOS film and a BPSG film. The method of claim 11, wherein the forming of the contact hole comprises: first etching the second insulating layer to expose the conductive layer pattern; Second etching the conductive layer pattern to expose the first insulating layer; And tertiary etching the first insulating layer to expose the gate and impurity regions. 19. The method of claim 18, wherein the conductive film pattern is exposed at both sides of the contact hole formed on the impurity region and connected to the second wiring layer. 12. The method of claim 11, wherein the first conductivity type is n-type and the second conductivity type is p-type. 12. The method of claim 11, wherein the first conductivity type is p-type and the second conductivity type is n-type.