KR0140473B1 - Method of forming the wiring on the semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-layer conductive wiring of a semiconductor device and a method of manufacturing a semiconductor device having the same, wherein the lower conductive wiring defined by an etch barrier layer pattern is defined as one side, and the upper conductive layer overlaps each other on one side of the lower conductive wiring. Since the conductive wiring is formed by the double layer structure of the wiring, and it is applied to the binary gate electrode formed over the different Morse field effect transistors of different conductivity types, the binary polysilicon layer gate electrode is formed. For example, a process such as a contact is omitted, the structure is simple, and the process yield is improved, and a separate contact area is not required, which is advantageous for high integration of the device.

Description

Double-layer conductive wiring of semiconductor device and method of manufacturing semiconductor device having same

1 is a layout view of a double-layer conductive wiring according to the present invention

2A and 2C are manufacturing process diagrams of the double-layer conductive wiring according to the present invention.

3 is a layout view of a semiconductor device having a two-layer conductive wiring according to the present invention.

4A and 4D are manufacturing process diagrams of a semiconductor device having a two-layer conductive wiring according to the present invention.

* Explanation of symbols for main parts of the drawings

A: active area mask C: P ⁺ ion implantation mask

D: N ⁺ ion implantation mask

1: semiconductor substrate 2: device isolation insulating film

3: gate oxide film 4, 400: first conductive layer

4A: P-type gate electrode 4B: N-type gate electrode

15: P ⁺ type source / drain electrode 20: etching barrier layer

25: N ⁺ type source / drain electrodes 30, 500: 2nd full layer

40: first conductive wiring mask 45: first gate electrode mask

50: second conductive wiring mask 55: second gate electrode mask

100: N type well area 200: P type well area

300: insulating film

The present invention relates to a two-layer conductive wiring of a semiconductor device and a method for manufacturing a semiconductor device having the same. In particular, one side of the conductive wiring is composed of a single layer and the other side is composed of two layers, so that the process yield is improved, and there is no separate connection device. The present invention relates to a two-layer conductive wiring of a semiconductor device, which is advantageous for high integration, and a method of manufacturing a semiconductor device having the same.

As semiconductor devices become more integrated, gate electrodes of metal oxide semi-conductor (MOS) field effect transistors are decreasing in width, but when the width of gate electrodes is reduced by N times, the electrical resistance of gate electrodes is increased by N times. There is a problem of reducing the operation speed of. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, was utilized as a low-resistance gate by using the characteristics of the polysilicon layer / oxide layer showing the most stable MOS field effect transistor characteristics. A low resistance gate may be formed by laminating a high melting point metal layer such as tungsten on the layer.

However, in the gate electrode in which the high melting point metal is laminated, the high melting point metal penetrates into the gate insulating layer in the high melting point metal layer forming process to increase the interface level or the fixed charge, and oxidize to the solid solution metal in the high temperature heat treatment process after forming the gate electrode. In order to solve this problem, there are studies to improve the high-melting point metal film, to improve the method of forming the high-melting point metal film, or to prevent oxidation by heat treatment in an H ₂ O / H ₂ mixed gas atmosphere. have.

In addition, as semiconductor devices are highly integrated, a complicated multilayer structure conductive interconnection interconnecting the devices is provided, which increases the complexity of the process, reduces the process yield, and makes high integration difficult.

In addition, polysilicon gate electrodes doped with P and N-type impurities are used to reduce the channel length of the P and N-MOS field effect transistors as the device is highly integrated.

However, in the semiconductor device as described above, one gate electrode line is simultaneously used as the gate electrode of the P and N-MOS field effect transistors. At this time, P and N-type impurities are ion-implanted into each portion and these portions are separated by separate connection lines. Connect it and use it.

The semiconductor device having the conventional binary polysilicon gate electrode as described above and a method of manufacturing the same have a complicated process because of the two-step impurity ion implantation process and a separate contact device to be formed. Due to the area occupied by the device, high integration of the device becomes difficult.

Accordingly, the present invention is to solve the above problems, the object of the present invention is to form a two-layer conductive wiring consisting of a single layer on one side and two layers by using an etching barrier layer pattern to improve the process yield and The present invention provides a method for manufacturing a double-layer conductive wiring of a semiconductor device, which is advantageous for high integration.

Another object of the present invention is to define a gate electrode using an etch barrier layer and a second gate electrode mask superimposed on a binary polysilicon gate electrode, and to form a top conductive wiring connecting both gate electrodes, P and N-type impurities are injected to both sides of the gate electrode by using the drain electrode mask to simplify the process, and the area of the contact device is reduced, thereby providing a method for manufacturing a semiconductor device having a two-layer conductive wiring, which is advantageous for high integration of the device. Is in.

In order to achieve the above object, the present invention provides a method for manufacturing a double-layer conductive wiring of a semiconductor device, including: forming a first conductive layer on an insulating substrate, and forming an etch barrier layer on the first conductive layer. Forming a first conductive wiring mask on the etch barrier layer, the first conductive wiring mask protecting a portion of the first conductive layer, which is intended for lower conductive distribution, and the first barrier wiring layer exposed by the first conductive wiring mask. Forming an etch barrier layer pattern to remove the first photoresist layer pattern; forming a second conductive layer on the entire surface of the structure; and a portion of the second conductive layer that is intended as the upper conductive wiring. Forming a second conductive wiring mask on the substrate; and etching the second conductive layer exposed by the second conductive wiring mask, and then again exposing the second conductive wiring mask and the etching barrier layer pattern. And removing the first conductive layer, wherein the first conductive layer is formed of a single layer conductive wiring and the second conductive layer pattern is formed of a second conductive layer pattern.

A semiconductor device manufacturing method including a two-layer conductive wiring according to the present invention for achieving another object is to form a gate oxide film on P and N type well regions separated by a device isolation insulating film formed on a semiconductor substrate. A process of forming, a process of forming a first conductive layer on the entire surface of the structure, a process of forming an etch barrier layer on the first conductive layer, and a portion of the first conductive layer that is intended as a binary gate electrode. Forming an etch barrier layer pattern to protect the gaps and to expose the connection portions therebetween; and covering an exposed portion between the etch barrier layer patterns at a portion of the first conductive layer, which is intended as a binary gate electrode. Forming a two-conductive layer pattern, and implanting P-type impurities into one end of the first conductive layer and the N-type well region on both sides thereof to form a P-type gate electrode and a P-type diffusion region And forming an N-type gate electrode and an N-type diffusion region with N-type impurities in the P-type well region at the other end and both sides of the first conductive layer.

Hereinafter, a double-layer conductive wiring of a semiconductor device according to the present invention and a manufacturing method of a semiconductor device having the same will be described in detail with reference to the accompanying drawings.

1 and 2A to 2C are layout views of double-conductor wirings of a semiconductor device according to the present invention and manufacturing process diagrams of cross sections along the line X-X 'in FIG.

First, the first conductive layer 400 to be a lower conductive wiring is formed on a predetermined insulating film 300 such as an interlayer insulating film or a planarization layer, and then etched with a subsequent laminated film on the first conductive layer 400. An etching barrier layer 20 made of a material having a large selectivity difference, for example, an oxide film, is formed. Next, a first conductive wiring mask 40 having a rectangular shape, which is intended to be a lower conductive wiring on the first conductive layer 400, is formed on the etching barrier layer 20 as a photosensitive film pattern. (See FIG. 2A) .

Thereafter, the etching barrier layer 20 exposed by the first conductive mask 40 is removed to form a pattern of the rectangular etching barrier layer 20 extending in one direction, and then the first conductive wiring line is formed. The mask 40 is removed, and the second conductive layer 500 is formed on the entire surface of the structure. Next, a second portion of the second conductive layer 500 that protects a predetermined shape, for example, a rectangular upper conductive wiring extending to one side and overlaps the pattern of the etching barrier layer 20 with the other side. The conductive wiring mask 50 is formed.

In this case, the first and second conductive layers 400 and 500 are different materials, for example, when the first conductive layer 400 is a silicon layer, the second conductive layer 500 is a silicide or tungsten layer. When the first conductive layer 400 is made of aluminum, the second conductive layer 500 is formed of a tungsten layer or a TiN layer (see also FIG. 2B).

Thereafter, the second conductive layer 500 exposed by the second conductive wiring mask 50 is removed to form an upper conductive wiring having a second conductive layer pattern.

In addition, one side of the first conductive layer 400 is connected by removing the first conductive layer 400 exposed by the etching barrier layer 20 pattern and the second conductive wiring mask 50. A lower conductive wiring pattern is formed (see also 2C).

The lower conductive wiring of the two-layer conductive wiring is a normal conductive wiring or a resistance wire or a conductive material having a relatively high resistance, or formed of a conductive material having low corrosion resistance, abrasion resistance, and the like, and is protected by an etch barrier layer. The upper conductive wiring overlapping the lower conductive wiring may be formed of a material having excellent mechanical and electrical properties such as corrosion resistance.

3 and 4A to 4D are views showing the layout of a semiconductor device having a double-layer conductive wiring according to the present invention and a manufacturing process diagram of a cross section different from the line Y-Y 'in FIG.

First, N and P type well regions 100 and 200 are formed on one side and the other side of the semiconductor substrate 1, respectively, and boundary portions of the N and P type well regions 100 and 200 and the semiconductor substrate are formed. An isolation region 2 is formed in a predetermined portion of (1) with an active region mask A of FIG. 3 to define an active region, and the gate oxide film 3 is formed on an exposed portion of the semiconductor substrate 1. After forming, the first conductive layer 4 and the etching barrier layer 20, which are lower conductive layers, are sequentially formed on the entire surface of the structure. In this case, the first conductive layer 4 is formed of polycrystalline or amorphous silicon, and the etch barrier layer 20 is formed of an oxide film. Thereafter, a portion of the first conductive layer 4 that is intended to be a dual gate electrode is protected and a first gate electrode mask 45 spaced by a predetermined interval in the middle is formed on the photoresist layer 20. (See also section 4A).

Thereafter, the etch barrier layer 20 which protects the portion of the first conductive layer 4 which is intended as the dual gate electrode is removed by removing the etch barrier layer 20 exposed by the first gate electrode mask 45. After the pattern is formed, the first gate electrode mask 45 is removed, and the second conductive layer 30 is formed on the entire surface of the structure. Next, a second gate electrode mask 55 is formed as a photoresist pattern to protect a portion of the second conductive layer 30 that is intended to be an upper roughness wiring line, that is, a portion spaced apart between the patterns of the etch barrier layer 20. (See also section 4B).

Thereafter, the second conductive layer 930 exposed by the second gate electrode mask 55 is removed to form upper conductive wiring, and the first conductive layer exposed by the etching barrier layer 20 pattern ( 4) the gate electrode extending over the N and P well regions 100 and 200 formed of the lower conductive wiring connected by the upper conductive wiring to the gate oxide film 3 and the device isolation insulating film. (2). (See FIG. 4C.)

Then, using a P ⁺ type ion implantation mask (C) shown in FIG. 3, P type impurities, for example, are formed on one side of the first conductive layer 4 pattern and the N type well region 100 exposed therefrom. For example, B is implanted at a high concentration to form a P-type gate electrode 4A on one side of the first conductive layer 4 pattern, and P ^{+ in} the N-type well region 100 on both sides of the P-type gate electrode 4A. The source / drain electrodes 15 are formed.

Then, using the N ⁺ ion implantation mask D shown in FIG. 3, an N-type impurity, for example, is formed on the other side of the first conductive layer 4 pattern and the P ⁺ type well region 20 exposed by it. For example, by implanting As at a high concentration, an N-type gate electrode 4B is formed on the other side of the exposed first conductive layer 4, and a P-type well region 200 is formed on both sides of the N-type gate electrode 4B. An N ⁺ type source / drain electrode 25 is formed (see also 4D).

As described above, the two-layer conductive wiring of the semiconductor device according to the present invention and the method of manufacturing a semiconductor device having the same include a lower conductive wiring defined by an etching barrier layer pattern on one side, and one side of the lower conductive wiring on one side. Conductive wiring is formed by a double layer structure of overlapping upper conductive wiring, and it is applied to binary gate electrodes formed over different Morse field effect transistors to form binary polysilicon layer gate electrodes, thus connecting upper and lower conductive wirings. The separate process, for example, a process such as a contact is omitted, the structure is simple, the process yield is improved, there is an advantage that the high integration of the device is advantageous because a separate contact area is not required.

Claims (7)

Forming a first conductive layer on the insulating substrate, forming an etch barrier layer on the first conductive layer, and protecting a portion of the first conductive layer on the etch barrier layer, which is intended to be a lower conductive wiring. Forming a first conductive wiring mask, forming an etch barrier layer pattern by removing the etch barrier layer exposed by the first conductive wiring mask, and removing the first conductive wiring mask; Forming a second conductive layer on the entire surface, forming a second conductive wiring mask on a portion of the second conductive layer that is intended as an upper conductive wiring, and being exposed by the second conductive wiring mask. The second conductive layer is etched, and the first conductive layer exposed by the second conductive wiring mask and the etch barrier layer pattern is etched. 1st Challenge Second conductive wiring method for fabricating a semiconductor device including a step of forming a conductive wiring pattern. 2. The method of claim 1, wherein the first conductive layer is a silicon layer and the second conductive layer is a silicide layer. 2. The method of claim 1, wherein the first conductive layer is a silicon layer and the second conductive layer is a tungsten layer. The method of claim 1, wherein the first conductive layer is aluminum and the second conductive layer is a tungsten layer. The method of claim 1, wherein the first conductive layer is aluminum and the second conductive layer is a TiN layer. The method of claim 1, wherein the etch barrier layer is an oxide film. Forming a gate oxide film on the P and N type well regions separated by an element isolation insulating film formed on the semiconductor substrate, forming a first conductive layer on the entire surface of the structure, and Forming an etch barrier layer pattern on the conductive layer, protecting the portion scheduled as the binary gate electrode in the first conductive layer and exposing a connection portion therebetween; Forming a second conductive layer pattern covering an exposed portion between the etch barrier layer patterns in a portion of the conductive layer, which is supposed to be a binary gate electrode, and an N-type well at one end and both sides of the first conductive layer; Forming a P-type gate electrode and a P-type diffusion region by ion implanting P-type impurities into the region; and N-type gate electrode as N-type impurities in the P-type well region on the other end and both sides of the first conductive layer. The method of producing a semiconductor device comprising a step of forming an N-type diffusion region.