JPS60148118A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60148118A JPS60148118A JP339684A JP339684A JPS60148118A JP S60148118 A JPS60148118 A JP S60148118A JP 339684 A JP339684 A JP 339684A JP 339684 A JP339684 A JP 339684A JP S60148118 A JPS60148118 A JP S60148118A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- dummy patterns
- gate
- patterns
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007772 electrode material Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 abstract 2
- 229910019213 POCl3 Inorganic materials 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 208000031513 cyst Diseases 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 241000238814 Orthoptera Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- VWDWKYIASSYTQR-UHFFFAOYSA-N sodium nitrate Chemical compound [Na+].[O-][N+]([O-])=O VWDWKYIASSYTQR-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、高信頼性、高生産性、高集積化を可能とした
ＭＯＳ型の半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a structure of a MOS type semiconductor device that enables high reliability, high productivity, and high integration.
近年、集積回路の集積度向上、素子の微細化が著しい。 In recent years, there has been a remarkable increase in the degree of integration of integrated circuits and miniaturization of elements.
ＡＩ ＯＳ型集積回路では、素子の微細化を進める上で
半導体基鈑やゲート電極材料のパターンニングを精度良
く行うためのエツチング技術、多層配線等を行うための
平担技術、微細パターンの光露光を行うための多層レジ
スト技術といったものが重要となる。In order to advance the miniaturization of devices, AI OS type integrated circuits require etching technology to precisely pattern semiconductor substrates and gate electrode materials, flattening technology to perform multilayer wiring, etc., and light exposure for fine patterns. Multi-layer resist technology will be important for this purpose.
しかし、この様な！轡にはパターン形状依存性という問
題点があった。But like this! The problem with this method is that it depends on the pattern shape.
すなわち、ゲート電極材料のパターンニングを行う場合
リアクティブ・イオン・エツチングの様な異方性エツチ
ング技術を用いても、第１図に示す様に、エツチング除
去する部分が他（７比べて広い所と隣接したパターンで
は、いわゆるサイドエツチングが生じ、加工寸法が、マ
スクパターンよりも小さくなる傾向がある。In other words, even if an anisotropic etching technique such as reactive ion etching is used to pattern the gate electrode material, as shown in Fig. In adjacent patterns, so-called side etching occurs, and the processing dimensions tend to become smaller than the mask pattern.
また、エツチングの様な平担化技術、多層レジスト技術
においても７第２図に示す様に基板あるいはゲート電極
材料のパターンニングでできた凹凸形状が影響し、前記
凹部が他と比較して広Ｖ１部分あるいはそれと隣接して
いる部分では、前記平担化技術、多層レジスト技術がう
まく効力を発揮しなかった。In addition, even in flattening techniques such as etching and multilayer resist techniques, as shown in Figure 2, the uneven shape created by patterning of the substrate or gate electrode material has an influence, and the recesses are wider than others. In the V1 portion or the portion adjacent thereto, the flattening technique and the multilayer resist technique were not effective.
特に、このことは半導体装置におけるメモリセルアレイ
のゲート電極のパターンニングの様な均一性を要求され
る場合（二大きな問題となっていた。In particular, this has become a major problem when uniformity is required, such as in the patterning of gate electrodes of memory cell arrays in semiconductor devices.
本発明はＪ□上記の如き問題を解決して、、生産性よく
半導体−町ヲ製造Ｔ、る事を可能とする半導体装■構□
造編提求す′４ｉを″目的とす６１’□〔発明の概要〕
、、、
本発明は、集積回路のマスクデザインを行うに■あたリ
パターンとパターンの間の距離がほぼ一定となる様にダ
ミーのパターン設ける１；！Ｉ”ｗ’＋＃徴とする。The present invention solves the above-mentioned problems and makes it possible to manufacture semiconductors with high productivity in a semiconductor device structure.
61'□ [Summary of the invention]
,,, The present invention provides mask design for integrated circuits by providing dummy patterns so that the distance between the two patterns is approximately constant1;! I"w'+# sign.
本発明によれば、ゲート電極等の加工寸法、が、サイド
エツチング、のパターン依存性によりばらつく事で住す
る素子特性のバラツキを低く励える事が可能となる。According to the present invention, it is possible to reduce variations in device characteristics caused by variations in processing dimensions of gate electrodes and the like due to pattern dependence of side etching.
、゛ ・
また、多層レジスト技術、ヱッテング技術が目的とする
平担化をより良く行う事が可能となる。,゛・In addition, it becomes possible to achieve better leveling, which is the goal of multilayer resist technology and etching technology.
従って、本発明によれば、生産性よくまた信頼性よく半
導性装置の一層の高集積化を図ることができる。Therefore, according to the present invention, it is possible to further increase the integration of semiconductor devices with high productivity and reliability.
〔発明の実施例〕
以下、本発明の実施例を第３図を用いて説明する。。第
３図は、不揮発性半等体メモリ装置の製造、轡、程Ｃ日
、おいて、本発明を用いてフローティングゲートアレイ
を形成した一例を表わしており、フローティングゲート
アレイαυの周囲にダミーパター′″′ごニー３−４つ
ｒｉｙ ｓ −ｙ＜ｙ −ｙ１１□３図囚−（Ａｔ’の
断面で考えると、たとえば第４図に示す様な工程で実現
でき・る。[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described using FIG. 3. . FIG. 3 shows an example in which a floating gate array is formed using the present invention during the manufacturing process of a nonvolatile semi-isolated memory device, and a dummy pattern is formed around the floating gate array αυ. If we consider the cross section of At', it can be realized, for example, by the steps shown in Fig. 4.
すなねち、シリコン基板Ｉ上にフィールド酸化膜ｔｔ４
ｖ形成後、ゲート酸化膜ｉｌｌ形成し、その上に、多結
晶シリコン層＋ｔｎを形成し、（′ｊＪ４図畠）、 Ｐ
ｑＣｌｓ ｋ用いた拡散仁よりリンを添加する。（１８
１、上記不純物を添加した多結晶シリコン層ｋＬ（シス
ト等（１１に一マスクＣ二（第ｊｌＪ、ｂ）二ツ〆ング
して浮遊ゲート（至）及びダミーパターン！２１１ｗ同
時に形成する。In other words, a field oxide film tt4 is formed on the silicon substrate I.
After V formation, a gate oxide film ill is formed, and a polycrystalline silicon layer +tn is formed on it, ('jJ4 Figure Hatake), P
Phosphorus is added via diffusion using qClsk. (18
1. A polycrystalline silicon layer kL (cyst, etc.) doped with the impurity described above (11) is covered with one mask C2 (jlJ, b) to simultaneously form a floating gate (to) and a dummy pattern!211w.
その後、上記レジストパターンを剥離して（第４図Ｃ）
第３図の様になる。After that, the above resist pattern is peeled off (Fig. 4C).
It will look like Figure 3.
このダミーパターンを設ける串により、たとえばゲート
電極材料のパターンニングを行った際、□パターン依存
性により、影＊Ｖ受ける１ｌｉｌ能性があるのはダミー
パターンになり、実際のゲート電極への影響は少くなる
。For example, when patterning the gate electrode material using the skewer provided with this dummy pattern, the dummy pattern has the potential to receive 1 lil of shadow *V due to pattern dependence, and the actual effect on the gate electrode is It becomes less.
なお第３図に示した／ ミニ／（タージ以外に、た七え
ばゲート電極パタニシと□同じダミーパターンでも、そ
の賜果は同じである。 □
また本発明は、エッチレグ皐多１ｍ７９．．）＄１２も
同様の賜果がある。 ′
それ＆＄５図を用いて説明する。すなわち、ダミーパタ
ーンシル設けるｊＩｉり第２図の場合と比較してエッチ
バッタや一層しシスト等の効力が増すことが判る。 °
″゛
本発明は、前記実施例以外書＝、たとえは酸化膜庫め込
み法を用いた素子分離−術（ＢＯＸ法）に″適用できる
。すなわち、第６図に示すように素子形成領域のパター
ンニングを行う際、ダミーパター・を設ける事により、
□その後の工程で、酸化膜９埋め込みを行う場釡用い６
瓦るエッチパック法に□よる平担化をよ□り良く行うｉ
が可能となる。比較のため従来例を第７図□に示す。In addition, the results are the same even with the same dummy pattern as the gate electrode pattern (in addition to the mini pattern shown in FIG. 12 has similar results. 'It&$5Explain using the diagram. That is, it can be seen that the effectiveness of etch locusts and cysts is increased compared to the case of FIG. 2 in which a dummy pattern sill is provided. °
``The present invention can be applied to devices other than the above-mentioned embodiments, for example, to element isolation techniques (BOX method) using an oxide film embedding method.'' That is, as shown in FIG. 6, when patterning the element formation region, by providing a dummy pattern,
□In the subsequent process, the oxide film 9 is filled in using the pot 6
Use the etch pack method to flatten the surface better.i
becomes possible. For comparison, a conventional example is shown in Fig. 7 □.
本発明はたとえばエレクトロン・ビーム′ｈ光を行う際
問題となる近接効果を抑える事にも有効である。近接効
果と龜、エレクトロン・ビームで描画を行う際、近接す
るニーター”ソの影響を受けて、均一にｉ画が行なわれ
外いというものである。□本発明により、ダミーパター
ンを設ける事＋、近接効果が一定に保たれ、したがって
均一な描画が可能となった。 ′The present invention is also effective in suppressing the proximity effect, which is a problem when using electron beam 'h light, for example. When writing using the proximity effect, electron beam, or electron beam, the i-drawing cannot be performed uniformly due to the influence of the nearby niter beam.□The present invention provides a dummy pattern + , the proximity effect was kept constant, and uniform drawing was therefore possible.'
第五図は、ゲー’） ’ｔ’ｔ＝材料のパターンニング
を行う際の問題点を示す断面図、第２図はエッチパック
あるいは多層レジスト等を行う際の間融煮ヲ示す断面図
、第３図は本発明の詳細な説明する平面図、第４図、第
５図、第６図及び第７図は本発明の詳細な説明する為の
断面図である。
因において、 ′ □
ｌ・・・半導体基板、 ２・・・シリコン酸化膜。
３・・・多結晶半導４膜、 ４・・・レジスト、′５・
・・ＲＸＥ、 ” ” ６・・・半導体基板、′７・・
・シリコン酸化膜、 ８・・・多結晶半纏体膜、９・・
・レジスト、 １１・・・フローティング伊ゲートアレ
イ、 １２・・・ダミーパターン、１３・・・フローテ
ィングｅゲート、
１４・・・８１基板、 １５・・・フィールド酸化膜、
１６・・・ゲート酸化膜、 １７・・・多結晶半導体、
１８・・・シンドープ多結晶半導体、
１９・・・レジスト、
２０・・・フローティング・ゲート、
２１．２２・・・ダミーパターン、
２３・・・多結晶半導体パターン、
２４・・・レジスト、２５・・・シリコン酸化膜、２６
・・・ダミーパターン、
２７・・・ソース・ドレイン及びチャネル領域、２８・
・・８１基板、 ２９・・・レジスト。
３０・・・シリコン酸化膜。
代理人 弁理士 則 近 憲 佑
（他１名）
第 ２ 図
第 ３ 図
第 ４ 図
ＣＣ）
第 ５ 図Figure 5 is a cross-sectional view showing problems when patterning materials, Figure 2 is a cross-sectional view showing intermittent melting when performing etch pack or multilayer resist, etc. FIG. 3 is a plan view for explaining the present invention in detail, and FIGS. 4, 5, 6 and 7 are sectional views for explaining the invention in detail. In the following, ′□l...semiconductor substrate, 2...silicon oxide film. 3...4 polycrystalline semiconductor films, 4...resist, '5.
・・RXE, ” ” 6...Semiconductor substrate, '7...
・Silicon oxide film, 8... Polycrystalline semi-coated film, 9...
・Resist, 11... Floating I gate array, 12... Dummy pattern, 13... Floating e-gate, 14... 81 substrate, 15... Field oxide film,
16... Gate oxide film, 17... Polycrystalline semiconductor,
18... Sin-doped polycrystalline semiconductor, 19... Resist, 20... Floating gate, 21.22... Dummy pattern, 23... Polycrystalline semiconductor pattern, 24... Resist, 25...・Silicon oxide film, 26
...Dummy pattern, 27...Source/drain and channel region, 28.
...81 substrate, 29...resist. 30...Silicon oxide film. Agent Patent attorney Kensuke Chika (and 1 other person) Figure 2 Figure 3 Figure 4 Figure CC) Figure 5
Claims (1)
ターンニング工程で、素子動作に関与しないパターンが
設けられた事を特徴とする半導体装置。A semiconductor device characterized in that a pattern that does not involve element operation is provided in a patterning process of a semiconductor substrate, an insulator, a gate electrode material, or a wiring material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP339684A JPS60148118A (en) | 1984-01-13 | 1984-01-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP339684A JPS60148118A (en) | 1984-01-13 | 1984-01-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60148118A true JPS60148118A (en) | 1985-08-05 |
Family
ID=11556197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP339684A Pending JPS60148118A (en) | 1984-01-13 | 1984-01-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60148118A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62123722A (en) * | 1985-11-22 | 1987-06-05 | Nec Corp | Semiconductor device |
| JPS636844A (en) * | 1986-06-26 | 1988-01-12 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5330311A (en) * | 1976-09-01 | 1978-03-22 | Fujitsu Ltd | Production of magnetic head of floating type |
| JPS5613747A (en) * | 1979-07-13 | 1981-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS5713180A (en) * | 1980-06-25 | 1982-01-23 | Fujitsu Ltd | Etching method |
| JPS57204146A (en) * | 1981-06-10 | 1982-12-14 | Toshiba Corp | Manufacture of semiconductor device |
-
1984
- 1984-01-13 JP JP339684A patent/JPS60148118A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5330311A (en) * | 1976-09-01 | 1978-03-22 | Fujitsu Ltd | Production of magnetic head of floating type |
| JPS5613747A (en) * | 1979-07-13 | 1981-02-10 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS5713180A (en) * | 1980-06-25 | 1982-01-23 | Fujitsu Ltd | Etching method |
| JPS57204146A (en) * | 1981-06-10 | 1982-12-14 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62123722A (en) * | 1985-11-22 | 1987-06-05 | Nec Corp | Semiconductor device |
| JPS636844A (en) * | 1986-06-26 | 1988-01-12 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPH0551171B2 (en) * | 1986-06-26 | 1993-07-30 | Kogyo Gijutsuin |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100536801B1 (en) | Semiconductor device and fabrication method thereof | |
| JP3164026B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100259078B1 (en) | Thin film transistor and method fabricating the same | |
| US8217465B2 (en) | Semiconductor constructions | |
| JPS6249750B2 (en) | ||
| US5728604A (en) | Method for making thin film transistors | |
| KR100190365B1 (en) | Semiconductor device manufacturing of photomask & forming method thereof | |
| JPS60148118A (en) | Semiconductor device | |
| JPS627535B2 (en) | ||
| JP3057837B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| KR19980053145A (en) | Manufacturing Method of Semiconductor Device | |
| JPS6046804B2 (en) | Manufacturing method of semiconductor device | |
| JP2557206B2 (en) | Method for manufacturing semiconductor device | |
| US3922704A (en) | Metal oxide semiconductor integrated circuit of reduced size and a method for manufacturing same | |
| KR100323717B1 (en) | Method for manufacturing of semiconductor device | |
| US4409727A (en) | Methods of making narrow channel field effect transistors | |
| JP2817226B2 (en) | Method for manufacturing semiconductor device | |
| KR100198632B1 (en) | Manufacturing method of semiconductor device | |
| JP2001068571A (en) | Method for fabricating embedded flash integrated circuit through simplified process | |
| JPS6211516B2 (en) | ||
| KR100239452B1 (en) | Method for manufacturing semiconductor device | |
| KR100250686B1 (en) | Manufacturing method of a semiconductor device | |
| KR100540332B1 (en) | Method for fabricating pattern of semiconductor device | |
| TW436908B (en) | Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits | |
| JPS647569A (en) | Manufacture of semiconductor nonvolatile memory |