JPS63205694A - Image reduction rotating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Industrial application field) The present invention provides angles of 90° and 180° with respect to the original image information.

The present invention relates to an image reduction and rotation circuit that creates reduced image information rotated by 2700 degrees. Especially the present invention.

The present invention relates to an image reduction and rotation circuit that creates and transfers reduced and rotated image data in the scanning direction when reducing and rotating image data on a memory that stores image information and transferring it to the outside.

(Prior art) Conventionally, when reducing and rotating two-dimensional information such as image information, first a memory area of the same size as the image is secured as a work area for image processing, and a processor is used to store the image in memory. Performs calculations to reduce the image data.

Thereafter, the image data is rotated by shift registers arranged in a grid pattern, and the image data rotated nine times is stored in the secured memory area. Thereafter, the data reduced and rotated in the scanning direction was read out and transferred. (Two circuits for rotating image information by 90° to 180° and 270° are disclosed, for example, in Japanese Patent Application No. 57-41879.) (Problems to be Solved by the Invention) Such image reduction rotation When a circuit handles a large amount of data such as image information, a memory area of the same size as the image to be processed is required as a work area for image processing. For this reason, when the image to be processed becomes large, a memory with an enormous memory area is required.

Also, if the length of data to be processed at one time becomes long.

The number of shift registers arranged in a grid pattern that rotates image data increases.

In this way, the image reduction rotation circuit described above.

The drawback is that the circuit scale increases as the image information to be handled increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image reduction/rotation circuit which eliminates the above drawbacks and can process large image information on a small circuit scale.

(Means for solving the problem) An image reduction rotation circuit according to the present invention includes an input data conversion circuit that reduces input data according to a reduction ratio and changes the arrangement of bit strings of the reduced data according to the angle of one rotation; a plurality of data shift circuits comprising a plurality of shift registers that simultaneously shift divided data of data into which bit strings have been converted; a plurality of RAM groups that temporarily store data rotated by the plurality of data shift circuits; and the input data. an output data conversion circuit that reads the output of the conversion circuit or data stored in the plurality of RAM groups and forms data for transfer as rotational image data in the scanning direction; and an address generation circuit that creates addresses for the RAM groups. and a timing generation circuit that generates timing for controlling each of the circuits.

(Example) Next, an example of the present invention will be described with reference to the drawings.

Referring to FIG. 1, an image reduction/rotation circuit according to an embodiment of the present invention reduces input data 1 according to reduction ratio information, rotates it by 90°, 180', or 2700 according to rotation angle information 6, and outputs data. It is output as n. This image reduction rotation circuit converts the original image into 72
An example will be explained in which the image is reduced by a factor of two and rotated 90 degrees to the left.

Input data 1 shown in FIG. 6 input data (FIG. 2(C) or FIG. 3(a)).

At this time, the reduction process in the scanning direction is performed by the input data reduction circuit 2.
This is done by thinning out, etc.

A thinning position of input data 10 is selected based on the reduction ratio information 24, and input data l is converted to reduced image data 3. As shown in Figure 2 (b), when performing 72 times reduction 1
The thinning process is performed every other dot.

Further, in the reduction process in the sub-scanning direction, the number of scanning lines is counted by a timing generation circuit.

The line to be thinned out selected by the reduction ratio information word is
And control is performed so that the second data shift circuits 5 and 6 do not receive the data. Alternatively, this can be done by detecting thinning lines by a higher-level micro-sequencer and controlling the input data of this circuit.

First and second data shift circuits 5 and 6 shown in FIG.
each consists of n m-bit shift registers. The first data shift circuit 5 is set with data shown in FIG. 3(a). At this time, the data set in the first data shift circuit 5 is converted into an input data conversion circuit based on input data 1 based on reduction ratio information and rotation angle information 25 (90' rotation). It is converted by 00.

The set data is converted by the shift register of the first data shift circuit 5 into rotated image data shown in FIG. 3(c). The converted data (rotated image data 7) is stored in a RAM buffer 9 as shown in FIG.
is written to the first RAM II for temporary storage. At this time.

The address color/rir continuously counts up.

Similar operations are performed by the second data shift circuit 6, RAM buffer 10, and second RAM 12.

FIG. 4 is a diagram showing conversion of a bit string by rotation of image data when two sets of data shift circuits 5 and 6 are used.

The original image data shown in Figure 4 (,) is N dots x M
Processed using dots as the basic area. In this example, M:
32 dots, N=16 dots.

The area of the N dora)XM dot is reduced by the input data reduction circuit 2 to the area of the n dora)Xm dot shown in FIG. 4(b). In this example, m=16 dots and n=8 dots. The area of the n dots (xm) shown in FIG. 4(b) is the basic processing area processed by the first and second data shift circuits 5 and 6. Figure 4 (C) is
The correspondence between the image data areas processed by the first and second data shift circuits 5 and 6 is shown. 1st and 2nd
In order to always operate the data shift circuits 5 and 6 simultaneously, data to be set is selected by the input data multiplexer 4 in consideration of the reconstruction of the two-rotation image data.

FIG. 4(,) shows the state of the rotated image data strings stored in the first and second RAM II and 12. The storage locations on the RAM of the data processed by the first and second data shift circuits 5 and 6 are determined in consideration of the reconstruction of one-rotation image data.

FIG. 4(f) shows an output data string when the reduced image data of FIG. 4(b) is rotated and transferred in the scanning direction. In order to create the output data string shown in FIG. 4(f), the address counter n shown in FIG. 1 is used as a counter whose count width is the bit length of the reduced image data 3. FIG. 4(g) shows the operation of the counter to obtain the output data string shown in FIG. 4(f).

The RAM data 13 and 14 that are simultaneously accessed and read from the temporary storage RAM II, 12 are converted into input data by an output data conversion circuit 200 consisting of a RAM data multiplexer 15, output registers 16 to 19, and an output data multiplexer 21. It is reconstructed as output data n having the same bit length as the bit length of 1. RAMII
, 12 because the rotated image data 7.8 are not stored continuously.

The data string is converted by the output data multiplexer 21. FIG. 4(h) shows the selection order of RAM output data to obtain the output data string of FIG. 4(f).

When the original image is reduced and rotated 90° to the right, the input data multiplexer 4 shown in FIG. 1 reversely converts the bit arrangement of the reduced image data 3. The converted data is set in the data shift circuit 5.6, and the same operation as the left 90' rotation is performed to obtain reduced and rotated image data.

When the original image is reduced and rotated 1800 times, the input data multiplexer 4 shown in FIG. 1 reversely converts the bit arrangement of the reduced image data 3. Converted 180°
The rotation image data I is.

The rotation angle information 5 is selected by the output data multiplexer 21 and output as output data n.

Furthermore, when only rotation processing is performed without performing reduction processing on the original image, input data 1 is input directly to input data multiplexer 4 without passing through input data reduction circuit 2 shown in FIG.

Control of each circuit section, address counter 27 (i.e.

RAM (other than 11.12) control 1ri, near 7
) 0-A, signal A, reduction ratio information and rotation angle information 5
, and is performed by a timing generation circuit A.

(Effects of the Invention) As described above, the present invention combines a small scale reduction circuit, a small number of shift registers, and a small number of RAM.
It is possible to perform image information reduction/rotation processing in which input data is reduced in the scanning direction and sent out. Furthermore, since a plurality of data shift circuits are operated simultaneously and a plurality of RAMs are accessed simultaneously, high-speed rotation processing can be performed.

Further, when increasing the bit length to be processed at one time, the selection can be made depending on the intended use, such as increasing the bit length of the shift registers of the data shift circuits 5 and 6 in FIG. 1, or increasing the number of data shift circuits.

Therefore, when applied to a circuit that sends data in the scanning direction, such as a reduction rotation processing circuit for a single display circuit, or a circuit that requires space-saving design with a small number of parts, the effect is significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image reduction and rotation circuit according to an embodiment of the present invention, FIG. 2 is a diagram for explaining data conversion by reduction of image data in the image reduction and rotation circuit of FIG. 1, and FIG. FIG. 4 is a diagram for explaining the conversion of a bit string by rotating image data in the image reduction/rotation circuit of FIG. 1, and FIG. 4 is a diagram for explaining the operation of the image reduction/rotation circuit of FIG. 1. In FIG. 1... Input data, 2... Input data reduction circuit. 3... Reduced image data, 4... Input data multiplexer, 5... First data shift circuit. 6... Second data shift circuit, 7.8... Rotating image data, 9.10... RAM buffer, 1
1... First RAM, 12... Second RAM,
13.14...RAM data, 15...RAM data multiplexer. 16-19...output register, 20...0°, 18
0° rotation image data, 21...output data multiplexer. n...Output data, 23...Control signal, 2
4... Reduction ratio information, 25... Rotation angle information, 26...
・Tie-up generation circuit, 27...address counter,
28...RAM address.

Claims (1)

[Claims] 1. In a circuit that reduces and rotates image data, an input data conversion circuit that reduces input data and changes the arrangement of bit strings, and a plurality of data consisting of a plurality of shift registers that simultaneously shift divided output data of the input data conversion circuit. a shift circuit, a plurality of RAM groups that temporarily store data rotated by the plurality of data shift circuits, and an output data conversion that forms rotated image data in the scanning direction by the data of the RAM group and the output of the input data conversion circuit. An image reduction rotation circuit comprising: a circuit, an address generation circuit for generating addresses for the RAM group, and a timing generation circuit for controlling each of the circuits.