JPS60171864A - Thinning-out method of picture data - Google Patents

Abstract

PURPOSE:To attain optional and minute thinning-out by setting a desired thinning-out pattern in X, Y directions and a thinning-out period to a register and thinning-out simply a data transferred from the set data. CONSTITUTION:A data transferred in a form of a serial signal is received by a receiver 2 and stored sequentially in a shift register 3. Then a line counter 10 counts the reception bit number at the same time and compares it with a preset line length register 11. When they are coincident, the result is given to a thinning-out pattern register 8 and shifted by 1 bit. A pattern thinned-out in the unit of lines is stored in a thinning-out period register 9 and gives a command to the thinning-out pattern register 8. A thinning-out period register 7 gives a command to a thinning-out pattern register for the period of the thinned-out pattern at each bit for a serial data stored in the shift register 3.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a system in which a large amount of data such as image data is transferred line by line as a serial signal, and the data transferred in the serial signal is It relates to a device that reduces and processes image data by thinning it in bit units in the direction and line units in the Y direction, and in particular can perform high-speed processing with a simple hardware configuration and can thin out image data in arbitrary patterns. Regarding the method.

(b) Prior Art and Problems Examples of devices that reduce and process large amounts of data, such as image data transferred line by line as serial signals, by thinning out the data include, for example, image data display devices or printing devices. When using software to process data sent from a host device, data is first stored in memory and then thinned out using a program in these devices. This method requires a large capacity memory to store a large amount of data such as image data, and it is not possible to perform fine thinning.Since the thinning is done in units of 1 pie or word, the reduction ratio is increased to reduce the image data to a small size. The disadvantage is that the thinning becomes rougher the more you do it. Furthermore, when processing with hardware, the thinning rate and thinning pattern are fixed, and there is a drawback that it is not possible to thin out to an arbitrary size with an arbitrary pattern.

(C) Object of the Invention An object of the present invention is to eliminate the above-mentioned drawbacks by providing a desired thinning pattern in the X direction and the Y direction, and Fine-grained and arbitrary thinning is possible by setting the thinning cycle in each register and simply thinning out the transferred data according to the specified thinning pattern in units of focus in the X direction and in units of lines in the Y direction. The object of the present invention is to provide a method for thinning image data.

(d) Structure of the Invention The structure of the present invention includes a shift register that stores data transferred by a serial signal, a first thinning period register that stores a thinning period in the X direction, and the first thinning period. a first thinning pattern register that stores a thinning pattern in which the number of shift stages to be circulated is determined by the register value; a second thinning period register that stores a thinning period in the Y direction; and a second thinning pattern register that stores a thinning period in the Y direction; a second thinning pattern register for storing a thinning pattern in which the number of shifting stages to be circulated is determined by the value of the thinning period register;
means for shifting the thinning pattern register;
The output of the first thinning pattern register is enabled only when the output of the thinning pattern register is "1" or "0", and the shift register is set so that the output of the first thinning pattern register is "1". or a shift register control means for controlling the shifting only when the value is 0'', and the shift operation of the shift register is controlled by the output signals of the first and second thinning pattern registers. It is.

(8) Embodiment of the Invention FIG. 1 is a block diagram of a circuit showing an embodiment of the invention. In this embodiment, in the receiving section of the interface section,
The case of thinning down to 8 bits will be explained.

The data transferred as a serial signal enters receiver 2,
The data are sequentially stored in the shift register 3 under the control of the shift register control section 5. At the same time, line counters 1 and 0 count the number of received bits and set the line length register 1 in advance.
It is compared with the value of 1 by the comparator 12. When the count value of the line counter 1o matches the value of the line length register 11, the comparator 12 sends a match signal to the line counter 10 and the thinning pattern register 8, the line counter 10 is cleared to zero, and the thinning pattern register 8 shifts by 1 bit. The decimation period register 9 instructs the decimation pattern register 8 how many bit periods should be used for the pattern to be decimated line by line. Therefore, the thinning pattern register 8 instructs the shift register control unit 5 to thin out the data stored in the shift register 3 line by line. The decimation cycle register 7 instructs the decimation pattern register 6 about the cycle of the pattern in which the serial data stored in the shift register 3 is decimated bit by bit. Therefore, the thinning pattern register 6 receives a synchronization signal synchronized with the shift cycle from the shift register control section 5, and instructs the shift register control section 5 to perform a thinning pattern in bits in synchronization with this synchronization signal. When the output of the thinning pattern register 8 is 1″, the shift register control unit 5
The output of the thinning pattern register 6 becomes valid, and the shift register 3 is shifted in accordance with the output of the thinning pattern register 6. Then, the output of thinning pattern register 8 is “0”.
”, the output of the thinning pattern register 6 becomes invalid and the shift register 3 does not shift. In other words, when the output of the thinning pattern register 8 is “0”, one line of received data is discarded and the output is “1”. In this case, the focus corresponding to the output of the thinning pattern register 6 of "0" in one line is discarded.The data sent from the shift register 3 is set in parallel in the output register 4 and sent to the bus. be done.

Figure 2 shows the thinning cycle register 7 and the thinning pattern register 6.
2 is a detailed block diagram of the thinning cycle register 9 and the thinning pattern register 8. FIG. That is, the thinning period registers 7 and 9 are composed of a 3-bit register 14 and a decoder 15, and the thinning pattern registers 6 and 8 are composed of an 8-bit shift register 1.
3 (for thinning down to 8 bits) and AND circuit 16~
22 and wired 08 circuit 23. The effective number of stages of the 8-bit shift register 13 is determined by the value previously placed in the 3-bit register 14 (for decimation to 8 bits). In the case of thinning pattern register 6,
The 8-bit shift register 13 synchronizes with the shift register 3 using a signal synchronized with the clock of the received data (as described above (given from the shift register control unit 5)), and receives one bit from fal to (h) every time it receives one bit. This is a register that shifts in the direction.In addition, in the case of the thinning pattern register 8,
The 8-bit shift register 13 is a register that shifts 1 bit (from al to (h) direction) by the match signal given from the comparator 12. This is the signal to open one of the gates.

That is, if it is 1000000, the AND circuit 22
000, AND circuit 21, 0010000, AND circuit 20, 0001000, AND circuit 1.
If 9 is 0000100, AND circuit 18 is 0000100.
If it is 0010, the AND circuit 17 can be turned on, and if it is 0000001, the AND circuit 16 can be turned on. Therefore, the number of shift stages of the 8-bit shift register 13 is determined, and the cycle is determined. For example, when 1' is given to the AND circuit 21 by the output of the decoder 15, the 8-bit shift register 13 becomes a 3-bit circulating shift register, and via the wired 08 circuit 23, the shift register control unit 5 receives tc+, (b), (a), tc+, (bl, (
A bit that changes periodically with al is sent out. Therefore, by writing a thinning pattern to the 8-bit shift register 13, thinning conditions can be set arbitrarily.

For example, in the case of 1/2 thinning, it is possible to obtain thinned data as shown in FIG. fJl'<10011100, indicated by 0, is placed in the 8-bit shift register 13. And as shown in the data string, the data string is 110100.
Suppose that it is 101111010001011011.

In order to set the period of the 8-bit shift register 13 to 2, the decoder 15 uses the value set in the 3-bit register 14.
When "1" is applied to the AND circuit 22, the thinning pattern is sent to the shift register control unit 5 as a focus repeating 0101, and the data string after thinning becomes 110011101101 as shown by the period ■. Further, when "1" is applied to the AND circuit 20, the thinning pattern becomes 1001 repetitions, and the data string after thinning becomes 110011000111 as shown by the period . Furthermore, AND circuit 16
If 1″ is given to , the thinning pattern is 00111001
This is repeated, and the data string after thinning becomes 010011000111 as shown in period (3).

Figure 4 shows image data divided by 2/3 in the X direction and 1/3 in the Y direction.
An example reduced to 2 is shown. When the thinning pattern is sent from the thinning pattern register 6 to the shift register control unit 5 at repetitions of 1011, and when the thinning pattern from the thinning pattern register 8 is sent to the shift register control unit 5 at repetitions of 1100, the original image In the X direction of the data 24, the bits in the shaded area are discarded, and in the Y direction, the lines in the shaded area are discarded, and the image data 25 is reduced to 2/3 in the horizontal direction and 1/2 in the vertical direction ( Be occupied.

(f) Detailed Description of the Invention As described above, the present invention can provide an image data thinning method that has a simple hardware configuration, has a high processing speed, and allows detailed and arbitrary thinning.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of the thinning period register 7, the thinning pattern register 6, the thinning period register 9, and the thinning pattern register 8, and FIG. FIG. 3 is a diagram illustrating thinned data, and FIG. 4 is a diagram showing an example in which image data is reduced to 2/3 in the X direction and 1/2 in the Y direction. 2 is a receiver, 3 is a shift register, 4 is an output register, 5 is a shift register control section, 6.8 is a thinning pattern register, 7.9 is a thinning period register, 10 is a line counter, 11 is a line length register, 12 is a comparator, 13 is an 8-bit shift register, 14 is a 3-pinto register, 1
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Claims (1)

[Claims] A shift register that stores data transferred by a serial signal, a first thinning period register that stores a thinning period in the X direction, and the number of shifting stages to be circulated is determined by the value of the first thinning period register. The first
A thinning pattern register, a second thinning period register that stores a thinning period in the Y direction, and a thinning pattern whose number of circulating shift stages is determined by the value of the second thinning period register. a second thinning pattern register; means for detecting one line of the serial signal and shifting the second thinning pattern register; and when the output of the second thinning pattern register is "1", and shift register control means for validating the output of the first thinning pattern register and controlling the shift register so as to thin out bits corresponding to the output of the first thinning pattern register being "0". . A method for thinning image data, characterized in that a shift operation of the shift register is controlled by output signals of the first and second thinning pattern registers.