JPH0584535B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to access control of a frame memory that stores image data, etc., a video memory that stores data to be displayed, and the like.

(Prior Art) Traditionally, dynamic memory (hereinafter referred to as "dynamic memory") has been used as a memory IC for devices that store large amounts of data such as image data, due to its advantages such as capacity and price.
DRAM) is mainly used. normal
DRAM has a structure in which each chip has one input/output terminal.
(m≧2) memory ICs are simultaneously driven to form a word configuration. In these conventional image memories, a data word is often configured as m pixel data consecutive in the horizontal direction, and when handling multi-valued (n-bit) image data, as shown in FIG. A plurality of sets (n sets) of these memory circuits are used to configure the entire image memory. The most important reason for adopting such a word structure of the memory is that speed conversion can be performed using a shift register in data input/output with the outside, as shown in FIG.

Inputting image data from scanners, TV cameras, etc., or outputting it to CRTs, printers, etc. is usually done in accordance with the operating speed of the input/output device, so high-speed data access is required for image memory. As shown in Figure 2, by converting serial to parallel (at input) and parallel to serial (at output) using a shift register, if the word structure of the memory circuit is m bits, the memory element itself The access speed of the memory IC decreases to 1/m of the serial data input/output speed.
becomes possible to use.

(Reference: Yasuji Suzuki, “CRT Daypress Technique”, Sanpo Publishing) (Problem to be solved by the invention) In the conventional memory circuit configuration, the unit of access to memory contents is always a memory word. The problem is that the unit is a certain number of m bits (=the number of stages of the shift register), and access is not possible with any number of dots smaller than that. As a result, it was not possible to perform operations such as data transfer on an area of any size and location on the memory. If you dare to rewrite one dot at a time in a memory circuit with such a configuration, you must first read out m bits x n sets of parallel output data from the memory circuit and store it in the buffer memory, then rewrite the required portion. However, it is necessary to rewrite the image data of m bits x n sets into the memory circuit again, which is not a sufficient solution in terms of processing speed and circuit configuration.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the conventional drawbacks and to enable access that is not constrained by the word structure of a memory with a simple circuit configuration.

(Means for Solving the Problems) The memory control circuit of the present invention is a memory circuit in which one word has m bits, and write signals to memory elements corresponding to each bit of one word are independent. When writing serial input data, first and second shift registers input write control data in synchronization with the input data and convert each data from serial to parallel into m bits; and means for detecting the end, and usually, when the serial-to-parallel converted input data and the write control data are paired in word units and the data is written into the memory circuit, and the end is detected, If the input data to the first and second shift registers is less than one word, the input to the second shift register is treated as non-write control data, and the input data to the first and second shift registers is written as non-write control data. clock, and also has a third shift register that converts m bits word by word from the memory circuit from parallel to serial when reading data serially, and converts the first word of data read from parallel to serial. If the valid data to be read into the third shift register during conversion is less than one word, input the remaining clocks to the third shift register, and then:
It outputs data.

(Function) With the above means, the unit of access to the contents of the memory circuit is not affected by the number of words of the memory, and can be accessed by any number of dots less than the number of words of the memory.

As a result, data transfer of an area of any size and location on the memory can be easily realized.

(Embodiment) An embodiment of the present invention is shown in FIGS. 1, 3 to 7.
This will be explained based on the diagram.

FIG. 1 is a block diagram of a memory control circuit of the present invention. In the figure, 1 is a memory circuit that stores image data, etc., and 2 is a memory circuit that serially stores write control data.
Shift register for parallel conversion; 3 is a shift register for serial-to-parallel conversion of input data; 4 is a shift register for parallel-to-serial conversion of data from memory; 5 is data indicating position information of input data, for example, a word of input data A write control circuit inputs data indicating the start and end of the input data and controls the clock and data given to shift registers 2 and 3 when writing data to the memory, and 6 is a shift register and data indicating the start of reading. A read control circuit inputs the output data from 4 and outputs read data in series with the clock applied to the shift register 4 when reading data from the memory; 7 is a memory data bus (1
8 is a write data bus (for 1 word) given to the memory circuit, 9 is a shift register 2,
10 is data given to shift register 3 (input data), 11 is data given to shift register 2 (write data), 12 is clock given to shift register 4, 13 is output data from shift register 4, 14 is serial input data (write data), 15 is data indicating the position information of the input data, for example, data indicating word division of data, data indicating the start and end of data, and 16 is serial output data ( data to be read), 17 is data indicating the position information of the output data, for example, data indicating word division of data, data indicating the start and end of data, and 18 is data indicating the contents of shift register 2, that is, shift register 2 This is data that sets the write control data output by ``non-write''.

FIG. 3 shows data on the memory, and words 1, 2, and 3 each represent one word of data in the memory. In the figure, a is a memory transfer area that can be realized in the conventional example, and b is a data transfer area that cannot be realized in the conventional example.

In the description of one embodiment of the present invention, a case will be described in which one word is 8 bits and data portions shown by diagonal lines in FIGS. 3a and 3b are written or read.

FIG. 4 shows the movement of control data and data to be written when writing the data in the shaded area in FIG. 3a, and FIG. 5 shows the data in the shaded area in FIG. 3b, respectively. In FIGS. 4 and 5, a indicates serial input data (data to be written), and the numbers indicate the order of transfer.
b is one word access data of position information for writing input data into the memory, and indicates a word division of the input data, and when the level is "H", the last data of the word is input to the shift register. Like b, c is also a type of positional information, and is status data indicating from the start to the end of input data, and the "L" level is the section. d
In FIG. 4, shift register 2 of FIG.
3 shows the data contents of shift register 3,
indicate the data contents of shift register 2, and A, B, and C in the figure represent word 1 and word 1, respectively.
Corresponds to 2 and 3. In FIG. 5, ' and ' also indicate the data contents of the shift registers 3 and 2, respectively. The numbers in d and ' indicate the correspondence with the data in a, data marked with "X" indicates uncertain data, ,' indicates write control data, "1" indicates "write", and in the figure A, B, C, and D indicate word 1, word 2, the contents of the shift register when data indicating the end is input, and word 3.

In addition, the data in the shaded area in Figure 3a is shown in Figure 6.
FIG. 7 shows the movement of the control data and the data to be read out when the data in the shaded area in FIG. 3b is read out, respectively.

In FIGS. 6 and 7, a and a' indicate the contents of the shift register 1 in FIG. 1. b is one word access data of position information for reading data, and indicates a word division of data. At "H" level, data is taken in from the memory and the first data of word data is output from the shift register. Similarly to b, c is also a type of positional information, and is data indicating from the start to the end of output data, and the "L" level indicates that section. d
is serial input data (data to be read), and the numbers indicate the order of transfer and correspond to the numbers in a. Data marked with an "X" in a and a' indicates unnecessary data (data that should not be read).

The operation of one embodiment of the present invention will be described below. 1 and 4, serial input data a, word access data b which is position information for writing, and status data c indicating data transfer from start to end are input to the write control circuit 5 ( 14, 15 in Fig. 1), and when the start of input data is recognized, the contents of shift register 2 are cleared (Fig. 1 18), that is, the output of shift register 2 (write control data) is set to "non-write". At the same time, write control data “Write” is input to the input of shift register 2 (Fig. 1 11).
Set. Thereafter, the input data is sequentially input to the shift register 3 in synchronization with the clock 9 (FIG. 1, 10). By inputting the same clock to shift register 2, input data 1
Shift register 3 when write control data corresponding to 0 is created in shift register 2 and data for one word is transferred to shift register 3.
The contents of shift register 2 are d, but the contents of shift register 2 are d.
becomes. At that time, word access data (FIG. 4d) indicating that the last data of one word has been input is input, and the contents of the shift register 3 are written into the memory circuit 1. In this case, all the contents of shift register 2 are "written", so all of the contents of shift register 3, that is, 1
Word (word 1) is written. In the case of writing word 2, data continues to be transferred from shift register 3, and when the last data of word 2 is transferred, the contents of shift registers 3 and 2 become the state of word 2 in FIG. 4d. , word access data b are input, so that the data of the contents of the shift register 3 is written into the memory circuit 1. Since the contents of shift register 3 at that time all indicate "write", word 2 is completely written. In writing of word 3, all data is written in the same way, but at the same time as the last data of word 3 is transferred, data c indicating that it is the last of the input data is also input, and the write operation ends. In this way, FIG. 4 shows that writing in word units can be realized in the same way as in the conventional example.

Next, in FIGS. 5 and 1, serial input data a, word access data b which is position information for writing, and status data c are input to the write control circuit 5 (FIGS. )death,
When the start of input data is recognized, the contents of shift register 2 are cleared (Fig. 18), that is, the output of shift register 2 (write control data) is set to "non-write", and at the same time the input of shift register 2 (write control data) is cleared. 1) Set the write control data "write" in FIG. 11). Thereafter, the input data is sequentially input to the shift register 3 in synchronization with the clock 9 (FIG. 1, 10). The contents of shift registers 3 and 2 at the time when word access data b, which is position information for writing and indicates the last data of a word, is input are as shown in d, that is, word access data. Until d is input, there are only 3 bits of input data 1, 2, and 3, and only that input data is transferred to shift register 3, and only the write control data for that input data is transferred to shift register 2. Only 3 bits serve as write control data for "write". Therefore, in word 1, only data 1, 2, and 3 are written to the memory circuit. In the case of writing word 2, as in the conventional example, serial input data is converted from serial to parallel for each word, and then writing is performed. Since all write control data in this case is "write", writing is performed in units of words. In the case of writing word 3, data is subsequently transferred to the shift register 3, but before one word is transferred, data c indicating that the input data is the last is input. The contents of shift register 3 at this point are C of d, and the contents of shift register 2 are C of d. In this state, the input data at the position to be written cannot be written into the memory circuit 1. Therefore, when data c indicating that the input data is the last is input, the input of shift register 2 is set to "non-write",
A clock for input data less than one word is input from the write control circuit 5 (in this case, since one word is 8 bits and the input data is 5 bits, a clock for 3 bits) is input. As a result, the contents of the shift registers 3 and 2 become as shown in d, and data is written to the memory circuit 1 at this point. As a result, all input data can be written to the desired writing location in the memory circuit 1. In this way, in one embodiment of the present invention, it is possible to write data in units of less than one word into the memory circuit, which could not be achieved in the conventional example.

Next, data reading will be explained. In FIG. 6 and FIG. 1, word access data b and status data c, which are data indicating position information for reading, are input to the read control circuit 6 (17 in FIG. 1). The data of word 1 is read out from the memory circuit 1 at the same time as the word access data b is input, and set in the shift register 4. The clock 12 is applied from the read control circuit 6, parallel to serial conversion is performed, and the data is converted into the word access data. At the same time, the status data also indicates the start of transfer, so the serial data from the shift register 4 is output from the read control circuit 6 as output data (FIG. 1, 16, and 6, d). Regarding word 2, the data is similarly read out from the memory circuit 1, converted from parallel to serial by the shift register 4, and the data is output in series (FIG. 6d). Similarly to words 1 and 2, data for word 3 is read from the memory circuit 1, converted from parallel to serial by the shift register 4, and output (FIG. 6d). After the last bit of data in word 3 is output, status data c indicates the end of the read data, and the read operation ends. In this way, FIG. 6 shows that word-by-word reading can be realized in the same way as in the conventional example.

Next, in FIGS. 7 and 1, word access data b and status data c, which are data indicating position information for reading, are input to the read control circuit 6 (17 in FIG. 1). From memory circuit 1, the data of word 1 is converted into word access data b.
It is read out simultaneously with the input of and set in the shift register 4. The data in the shift register 4 at that time is a, and then the clock 12 is applied from the read control circuit 6 to perform parallel to serial conversion. However, at the time the word access data b is input, the status data c does not indicate the start of reading, so the read control circuit 6 does not transmit the output data of the shift register 4 (see FIG. 1) until the start of reading is indicated. 13) is not output (Fig. 1, 16). When the status data c indicates the start of data reading, the data in the shift register 4 is a', and thereafter the output data 13 of the shift register 4 is output. As a result, in word 1, only three bits of data 1, 2, and 3 are output. In word 2, similar to what was explained in FIG. 6, from memory circuit 1,
The data is read out, converted from parallel to serial by the shift register 4, and is output in series (FIG. 7d). In word 3, word 2
Similarly, at the same time as the word access data is input, the data of word 3 is read from the memory circuit 1, set in the shift register 4, and read control circuit 6
A clock 12 is applied from , and the parallel to serial conversion is performed and output (Fig. 1, 13). Since the status data at that point indicates that the data is being transferred, the read control circuit 6 outputs the data (see FIG.
6, Figure 7 d). However, since the status data c indicates the end of data readout during the data transfer of word 3, the readout control circuit 6 ends the data output and ends the data readout operation when the end is recognized. In the case of FIG. 7, since 5 bits of word 3 data have been transferred, only those 5 bits are output.

In this way, in one embodiment of the present invention, it is possible to read data from a memory circuit in units of less than one word, which could not be achieved in the conventional example.

According to the above explanation, in one embodiment of the present invention, reading data in word units as in the conventional example,
In addition to writing, it is also possible to read and write data in units of less than one word.
For example, if one embodiment of the present invention is connected to a bus such as a CPU, when accessing a memory circuit as shown in FIG. 2, each memory circuit can be accessed bit by bit. If the depth direction (n sets) of the memory circuit in Figure 2 can be taken as one word of the CPU, and if that depth direction is the gradation data of the image data, then the CPU can access each pixel.
It becomes possible from

(Effects of the Invention) According to the present invention, there are various effects as follows.

(1) From the memory circuit that stores image data, etc.
Data reading and writing can be realized in units of less than one word of the memory circuit.

(2) Since we are dealing with serial input and output data,
There are few connection points with the outside, so it can be easily combined.

(3) By using the depth direction of the memory circuit as the gradation data of the image data and connecting it to the CPU bus, the CPU can access the memory circuit bit by bit, independent of the physical word structure of the memory circuit. possible, as CPU word data,
It can handle data in the gradation direction, and when performing arithmetic processing on image data,
General-purpose software can be applied to the CPU without being aware of the physical word structure of the image memory, and a memory circuit with high practical value can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control circuit according to an embodiment of the present invention, FIG. 2 is an example of a memory circuit, FIG. 3 is a block diagram of data in the memory circuit to be accessed, and FIG.
5 is a chart showing control data and write data in the case of data writing of the memory control circuit of the present invention, and FIGS. 6 and 7 are charts showing control data and write data in the case of reading the same. It is. 1... Memory circuit, 2, 3, 4... Shift register, 5... Write control circuit, 6... Read control circuit, 7, 8... Data bus, 9, 12... Clock, 10, 14... Input data, 11...Write data, 13, 16...Output data, 15,
17...Position information data, 18...Control data.

Claims (1)

[Claims] 1 One word is m bits, and when writing serial input data in a memory circuit in which write signals to memory elements corresponding to each bit of one word are independent, The first and second shift registers input write control data and convert each data from serial to parallel into m bits, and means for detecting the end of the input data, and when the end is detected. To,
If the input data to the first and second shift registers is less than one word, the input data to the second shift register is treated as non-write control data, and the first,
The second shift register has a third shift register which inputs the unfilled clock and converts m bits word by word from the memory circuit from parallel to serial when reading data serially.
If the valid data to be read into the third shift register during parallel-to-serial conversion of the first read data is less than one word, after inputting the unfilled clock to the third shift register, A memory control circuit characterized by outputting data.