JPS61167984A - Image memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image memory device characterized by access control from a micro ψ processor to an image refresh memory for recording and displaying multi-gradation images.

Prior Art Conventionally, memo IJI constituting the artist's refresh memory
As C, dynamic memory (hereinafter referred to as DRAM) is mainly used because of its advantages such as capacity 2 and price.

A normal DRAM has a structure with a 1-pit input/output terminal, so when configuring an image refresh memory, multiple memories, for example m (m≧2)
The m-phase drive method in which C is powered by the same control signal is common (CRT Display Techniques, written by Meikihe Junichi).
Sanpo Publishing, etc.). By performing m-phase driving, the display access cycle of the memory IC becomes m times the display dot clock, so there is an advantage that even a relatively low-speed memory can be used. FIG. 6 shows an example of the configuration of a typical conventional image refresh memory.

The image refresh memory 1 is composed of m memory ICs 2 (m=8 in the example shown in the figure) and has m data input/output lines 3.

For normal image display, the readout converter 4 sequentially reads out the contents of the image memory via the data input/output line 3.
This is done by performing parallel-to-serial conversion and converting into a video signal 6.

On the other hand, the contents of the image memory are updated by write access from a microprocessor circuit (hereinafter referred to as MPU circuit) 6. A data bus 7 of the MPU circuit 6 is coupled to a data input/output line 3 of the image memory via a bidirectional bus buffer 8.

The number m of driving phases of the image memory 1 is the number of display dots, and the number m of drive phases of the image memory 1 is
Although it is determined based on the cycle time of C, etc., it is common for the data bus 7 of the MPU circuit 6 to have a 1-byte or 2-byte word configuration, so the number of memory phases m is usually set to a multiple of 8. There are many things.

If the word length of the data on the data bus 7 of the MPU circuit and the word length of the data input/output line 3 of the artist memory 1, that is, the number of drive phases m, do not match, a data selector is sent to the bidirectional bus buffer 8. Differences in data word length are absorbed by methods such as providing a function as a data word and performing division processing. In either case, the MPU circuit 6 processes the information of 8 horizontal dots displayed in the image memory as 1 byte of data. The image memory is normally accessed by the read conversion unit 4 for display.

The bus arbiter 9 is a circuit that time-divisionally controls accesses from the read converter 4 and the MPU circuit 6 to the image memory 1.

Normally, access from the read converter 4 is given priority in order to update the memory contents without disturbing the display. A common method is to perform access from the MPU circuit 6 during a display blanking period. The address multiplexer 10 selects the display address 12 from the display control circuit 11 during the display period according to the signal from the bus arbiter 9, and selects the address signal 13 from the MPU circuit 6 during the blanking period, and selects the display address 12 from the display control circuit 11 during the display period and selects the address signal 13 from the MPU circuit 6 during the blanking period. 1 address signal 14. In order to access faster from the MPU circuit, the access cycle of the memory IC is divided into two or more cycles, and the access from the read converter 4 and the access from the MPU circuit 6 are alternated each time. (Interface)
7. August 1984 issue, CO Publishing).

In the above explanation, the image refresh memory has been described as an image refresh memory for storing and displaying binary image data, but when handling multi-value image data, conventionally the image refresh memory 1 shown in FIG. , readout converter 4, bidirectional bus buffer 8, and other components corresponding to the number of bits in the gradation direction (=n) of multivalued data, thereby serving as a refresh memory for multivalued images. However, access from the MPU circuit 6 is performed in units of bit planes via the bidirectional bus buffer 8.

Problems to be Solved by the Invention However, in the conventional access method from the microprocessor section of the image memory, the data on the data bus that is input/output to and from the image memory is not horizontal even when handling multilevel images. Directional display dot pattern data. On the other hand, a general data format inside a system that handles multivalued image data is data that expresses the gradation of each pixel.

Therefore, when inputting and outputting data between the MPU circuit and the image memory, it is necessary to convert the data format (the meaning of the data) each time. Furthermore, it is difficult to rewrite data pixel by pixel in the image memory, and a plurality of pixels in units of input/output data length (generally m dots) on the image memory side must be handled at once. In the development of software on the MPU circuit side, it has been pointed out that there is a problem in that versatility is impaired because special processing is required to access the image memory.

The present invention has been made in view of the above-mentioned problems.
While functioning as an image refresh memory, the MPU
The purpose of the circuit is to provide an image memory that can be accessed as regular RAM connected to a data bus.

Means for Solving the Problems The present invention aims to solve the above problems.When reading access from the microprocessor section to the image memory, n
Among the data input/output lines of the image memory consisting of m rows and m columns, n-bit data in the column direction of the first (i = 1 to m) column specified by the address output of the microprocessor section is sent to the microprocessor section. is applied to the data bus of the microprocessor, and is
Among the data input/output lines of the image memory consisting of m rows and m columns,
Only the n-bit data in the column direction of the first column specified by the address output of the microprocessor section is replaced with data from the microprocessor section, and the data in other columns is replaced with the data held before that. This constitutes an image memory device equipped with a data conversion circuit that controls the data to be written as is into the image memory.

Effects The present invention has the above-described configuration, and while functioning as an image refresh memory, the MPU circuit section can perform random access to gradation data for each pixel at any time, which is a very versatile image refresh memory. Memory can be realized.

Embodiment FIG. 1 is a block diagram showing an embodiment of an image memory device according to the present invention. The basic operation is the same as the conventional configuration example shown in FIG. 6, except for the data conversion circuit 18. In FIG. 1, reference numeral 11 denotes an image refresh memory (hereinafter referred to as image memory) constructed by using n sets of bit plane memories having m-phase drive and m-bit input/output terminals. Reference numeral 12 denotes data input/output lines of the image memory 11 consisting of n rows and m columns. Reference numeral 13 denotes a read conversion unit that performs display access, and converts data in the row direction (m bits/
n sets of words) are parallel-serial converted into n-bit serial image data 14. Serial image data 14 is converted into analog video signal 1 via DA converter 16.
6 and displayed.

On the other hand, the image memory 1 from the microprocessor section 17
Access to 1 is performed via data conversion circuit 18. The data conversion circuit 18 converts data input/output lines of the image memory 11 consisting of n rows and m columns into data in the column direction (n bits/word) corresponding to data in the gradation direction from m to 1.
The ninth day (1=1 to
Only data in the column direction of m) is connected to the data bus 21 of the microprocessor unit (hereinafter referred to as MPU circuit unit) 17, and data read/write access is performed.

A more specific example of the configuration of the data conversion circuit 18 will be described later. The bus arbiter 22, display control circuit 23, and address multiplexer 24 operate in the same manner as in the conventional example shown in FIG. 6, so detailed explanations will be omitted here.

In order to access from the MPU circuit unit 17 at high speed, it is preferable to perform memory control in two or more memory cycles.

FIG. 2 is a diagram showing a first embodiment of the data conversion circuit 18 according to the present invention. In the following explanation, the number of memory phases m = 16, the memory gradation n = 8 bits, and the MPU
The explanation will be given assuming that the data bus word length 1 of the circuit section 17 is 8 bits. The example in FIG. 2 is a diagram showing a portion of the data conversion circuit that processes data on the third (j=1 to 8) bit plane. In the example in the same figure, the memory IC
.

The bit plane memory 31 consisting of M1 to M1e is configured to operate in a read/write or read-modify-write cycle, so the data input line and data output line of each memory IC are separated. It is used. Therefore, even if m;16, the number of signal lines is 32. The data bus B t 32 is a signal corresponding to the fifth bit plane of the data bus of the MPU circuit section. The three-state gates 33 to 43 in the figure all maintain a high impedance state except when the control signal is true. Since external access to the image memory is always performed in units of 16 bytes (8 rows and 16 columns), the lower 4 bits of the address of the MPU circuit are M
This is an address for selecting 1 to M16. In order to access specific pixel data from the MPU circuit, it is necessary to decode the address of the MPU circuit section and create a selection control signal for selecting one specific column from 16 columns (16 bytes) of data. In the example shown in FIG. 2, it is sufficient to decode the lower 4 bits of the address output of the MPU circuit section.

As a decoding circuit, a TTLic (demultiplexer) such as 74138.7442 can be used.

81 to S16 are the selection control signals obtained in this way, 81 indicates that M1 is selected as the address, and S1 indicates that M1 is not selected. R
D is a signal indicating that the access from the MPU circuit section is in the read mode, and WT is a signal indicating that the access from the MPU circuit section is in the light fist mode.

Now, assuming that M2 is selected by address decoding, only the selection control signal S2 is true, and Sl
, 33 to S16 are all false, so during read mode access, only the three-state conflict gates 36 and 42 are in the ON state, and the output data of M2 is connected to the data bus Bt.

On the other hand, when accessing in write mode, 3 states,
The gates 34, 38, 40, and 43 are turned on, and the data on the data bus J is inputted only to the input terminal of M2 via the gate 38.

In the memory ICs other than M2, the data previously held in each memory 91C is rewritten via gates 34 and 40, respectively. The above operation is performed on each bit plane (
1; 1 to 8), it is possible to read/write only the data of an arbitrary pixel from the MPU circuit.

The selection control signals 81 to S16 can be used commonly for each pit plane. Further, Q, , -Q, 16 in FIG. 2 are output signals of the memory connected to the readout converter for display.

FIG. 3 is a diagram showing a second embodiment of the data conversion circuit constituting the image memory device according to the present invention. 61 is
It is a bit plane memory that operates with 16-phase drive, and the data lines of each memory IC are buffered with 3-state gates, and there are 16 data input/output lines (MD1 to MD16). Reference numeral 62 indicates a part of the data conversion circuit that processes data on a 1-bit plane, and the inside thereof is further composed of processing units T1 to T1e for each pit. Each processing unit consists of one D flip-flop and three three-state gates. The operation of the processing unit T1 in FIG. 3 will be explained with reference to the drawing. First, in the read mode from the MPU circuit, after the output data MD1 of the image memory is determined, the clock C
The output data of the memory is taken into the D flip-flop 53 by K57. According to the output of the decoded lower address (4 bits) of the MPU circuit, if memory M1 is selected, Sl becomes true, gate 56 is turned on, and the contents of MDl are transferred to data bus B1 of the MPU circuit. Given. If memory M1 is not selected, the output of T1 maintains a high impedance state and connects data bus B.
1 is not affected.

Next, in the write mode from the MPU circuit section, first read all memory contents, and
Outputs MD1 to M of the memory corresponding to flip-flops
Store D1s. Thereafter, rewriting to the memory is performed, and if memory M1 is selected as a result of address decoding, gate 66 is turned on and the contents of data bus B1 are applied to MD1. Since the gate 54 is in the off state at this time, the contents of the D flip clock have no effect on the MDI, and the memory contents are rewritten.

If the memory M1 is not selected, the gate 66 is turned off, the gate 64 is turned on, and the D clip flop 63 is turned off.
, that is, the contents previously held by memory M1. This series of operations makes it possible to access only the byte of data specified by the lower address out of the 16 bytes of data that are accessed at a time. Reference numeral 68 in FIG. 3 is a parallel-to-serial conversion circuit constituting the read conversion section, and although it is not a component of the data conversion circuit, it is shown to show the connection method.

The actual data conversion circuit is the bit plane unit processing part 5.
2 for 8 bits, a clock 67, a circuit for generating control signals for each gate, a circuit for controlling timing with the bus arbiter, etc.

The image memory 61 is accessed every memory cycle for display purposes, and access from the MPU circuit is performed during the display blanking period or by time-sharing a part of the memory cycle. Display memory/
Access timing is strongly restricted. However, the third
In the embodiment shown in the figure, since each bit of the data conversion circuit has a storage element, the data conversion circuit and the MPU
Communication with the circuit can be performed at any timing, asynchronously with display memory access. Also, light
In mode, one data conversion operation, such as reading the memory contents into the D flip-flop at the first image memory access and rewriting to the image memory at the next image memory access, is performed several times. This has the advantage of providing flexibility, such as over the access cycle.

FIG. 4 is a diagram showing a third embodiment of the data conversion circuit according to the present invention. Reference numerals 71 to 78 denote bit plane memories, each of which is composed of one printed circuit board for each bit plane.

62 is a data conversion circuit, and its basic configuration is the same as that shown in the example of FIG. 3, but in the example of FIG. 4, a memory 63 is used as a storage element, and the data conversion circuit are configured to process all bit planes in one set. In the example shown in the figure, the same data input/output lines (MD1 to MD16) of eight bit plane memories are wire-connected and each connected to the memory 63 of the data conversion circuit 62.

The data conversion operation is performed on the bit plane sequentially. The operation in read mode will be explained. Bit plane B1
Assuming that processing is performed in the order from B8 to B8, first, if control signals D1 and RD of the bit plane memory 71 are controlled to be true and the control signals of the other bit plane memories are false, the output of the bit plane memory 71 will be Only signals MD1 to MD1e are input to data conversion circuit 62. At this time, the data output of other bit plane memories is 3
Blocked by state gate M D 1 qDl 6
does not affect. Here, if the memory M1 is selected by the address output of the MPU circuit, only MD1 of the memory output signals MD1 to MD16 input to the data conversion circuit 62 passes through the gate 66, and the latch circuit 68
The data bus B1 of the MPU circuit is latched to the data bus B1 of the MPU circuit through a gate 69.

Next, processing is transferred to the bit plane B2, where MDl of the memory outputs of the bit plane memory 72 is latched by the latch circuit 80 and sent to the data bus B2 of the MPU circuit by the gate 81.
connected via. Below, in the same procedure, bit plane B
When the data of 8 is latched by the latch circuit 82, it becomes 1
Read byte worth of data into the MPU circuit.

Next, in the write mode, data B1 to B8 on the data bus of the MPU circuit are first transferred to latch circuits 91.92 to 91.92.
Latch to 98. Next, the memory outputs of all the bit plane memories are taken into the memory 63 in the data conversion circuit in a field-sequential manner using the same procedure as in the read mode. At that time, M
By the address output of the PU circuit, for example, memory M1
is selected, only the memory 63 of the processing unit (TI) corresponding to the memory M1 has the gate 67 turned off and the gate 66 turned on, so that the MPU outputs the image memory output MD1 instead of the image memory output MD1. The output that latches data on the circuit's data bus is connected. That is, in the case of bit plane B1, the output of the latch circuit 83 is
In the case of bit plane B2, the outputs of the latch circuits 84 are connected through the respective control gates.

In the processing units other than t1, the gate 67 is on and the gate 66 is off, and the output of the image memory (MD2 to MD
16) are taken into each memory 63. Bit address 70, which is the address signal of memory 63, is
It may also be binary data specifying bit planes B1 to B8.

Bit address 70 corresponds to all processing units D1~
This is common to the memory 63 of T16. As a result of the above operation, among the memories in the data conversion circuit 62, the memories other than the processing unit T1 have the output MD2 of the image memory.
~16 bytes of data from MD16 are stored in the memory of processing unit T1, which is data output from the MPU circuit.
Bytes of data are temporarily stored. Next, the contents of the memory 63 are rewritten into image data in a frame-sequential manner. At this time, the gate 64 is turned on, the output of the memory 63 is connected to the image memory, and data is sequentially rewritten into the bit plane memories 71 to 78.

As is clear from the above explanation, by adopting the configuration of the data conversion circuit as shown in FIG.
The purpose of freely accessing any pixel data in the image refresh memory can be achieved. Fourth
In the example shown in the figure, each of the data input/output lines MD I -MD 16 of eight bit plane memories can be connected by wire, so great advantages can be obtained in terms of mounting such as board arrangement and wiring.

Effects of the Invention As described above, according to the present invention, an image refresh function that constantly displays an image can be achieved with a simple circuit configuration.
The memory can be used as an image memory device that can be freely accessed as a normal RAM without being concerned about image display timing or data format.

In software development, it can be expected to have great industrial effects, such as being able to apply general-purpose image processing software as it is, since it does not require any special access method even though it is an image display memory. Although several embodiments have been given as the method of configuring the conversion circuit, the method of construction is not limited to these, and it is of course possible to apply an application method such as converting the circuit into an IC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image memory device according to an embodiment of the present invention, FIGS. 2 to 4 are configuration diagrams for explaining each embodiment of a data conversion circuit according to the present invention,
FIG. 6 is a block diagram showing the configuration of a conventional image memory device. 11... Image memory, 13... Read conversion section, 17... Microprocessor section, 1
8...Data conversion circuit, 21...Data bus. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure data bus ej Figure 5

Claims (2)

[Claims] (1) A memory circuit driven by m phases (m≧2) and having m-bit data input/output lines is used as a bit plane memory, and n sets (n≧2) of these bit plane memories are provided with 2n gradations (
an image memory configured to record gradation data of 1 bit (l≧n); and a microprocessor unit having a data bus, and when the microprocessor unit reads the image memory, the address of the microprocessor unit is selected from among the data input/output lines of the image memory consisting of n rows and m columns. n in the column direction (gradation direction) of the i-th (i=1 to m) specified by the output
Controls bit data to be provided on the data bus of the microprocessor section, and when the microprocessor section writes access to the image memory,
Of the data input/output lines of the image memory consisting of n rows and m columns, only n-bit data in the i-th column direction (gradation direction) specified by the address output of the microprocessor section is sent to the microprocessor. The image forming apparatus is characterized in that it is equipped with a data conversion circuit that performs control so that the data in the other columns is replaced with the data on the data bus of one column, and the data in the other columns is written into the image memory as the data previously held. memory device. (2) The data conversion circuit has a storage element of n×m bits or more, and a write access to the image memory from the microprocessor section is a read access from the data conversion circuit to the image memory and a write access to the image memory from the microprocessor section. 2. The image memory device according to claim 1, wherein the image memory device is performed by write access to the image memory from a subsequent data conversion circuit.