JPS63201825A - 演算処理装置 - Google Patents

演算処理装置

Info

Publication number
JPS63201825A
JPS63201825A JP62035042A JP3504287A JPS63201825A JP S63201825 A JPS63201825 A JP S63201825A JP 62035042 A JP62035042 A JP 62035042A JP 3504287 A JP3504287 A JP 3504287A JP S63201825 A JPS63201825 A JP S63201825A
Authority
JP
Japan
Prior art keywords
numbers
multiplier
multiplication
product
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62035042A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0583930B2 (enrdf_load_stackoverflow
Inventor
Tamotsu Nishiyama
西山　保
Tadashi Takagi
高木　直史
Shigero Kuninobu
國信　茂郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62035042A priority Critical patent/JPS63201825A/ja
Priority to US07/095,525 priority patent/US4868777A/en
Publication of JPS63201825A publication Critical patent/JPS63201825A/ja
Priority to US03/239,243 priority patent/US5031136A/en
Priority to US07/599,275 priority patent/US5153847A/en
Publication of JPH0583930B2 publication Critical patent/JPH0583930B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
JP62035042A 1986-06-27 1987-02-18 演算処理装置 Granted JPS63201825A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62035042A JPS63201825A (ja) 1987-02-18 1987-02-18 演算処理装置
US07/095,525 US4868777A (en) 1986-09-12 1987-09-10 High speed multiplier utilizing signed-digit and carry-save operands
US03/239,243 US5031136A (en) 1986-06-27 1990-05-07 Signed-digit arithmetic processing units with binary operands
US07/599,275 US5153847A (en) 1986-06-27 1990-10-16 Arithmetic processor using signed digit representation of internal operands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62035042A JPS63201825A (ja) 1987-02-18 1987-02-18 演算処理装置

Publications (2)

Publication Number Publication Date
JPS63201825A true JPS63201825A (ja) 1988-08-19
JPH0583930B2 JPH0583930B2 (enrdf_load_stackoverflow) 1993-11-30

Family

ID=12430983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62035042A Granted JPS63201825A (ja) 1986-06-27 1987-02-18 演算処理装置

Country Status (1)

Country Link
JP (1) JPS63201825A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511981A (ja) * 1990-08-07 1993-01-22 Matsushita Electric Ind Co Ltd 乗算処理装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511981A (ja) * 1990-08-07 1993-01-22 Matsushita Electric Ind Co Ltd 乗算処理装置

Also Published As

Publication number Publication date
JPH0583930B2 (enrdf_load_stackoverflow) 1993-11-30

Similar Documents

Publication Publication Date Title
US4168530A (en) Multiplication circuit using column compression
US7308471B2 (en) Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
JPS60229140A (ja) 倍精度乗算器
US4868777A (en) High speed multiplier utilizing signed-digit and carry-save operands
JPS6375932A (ja) ディジタル乗算器
JPS588009B2 (ja) デイジタル乗算器
US3805043A (en) Serial-parallel binary multiplication using pairwise addition
US5944776A (en) Fast carry-sum form booth encoder
KR100308726B1 (ko) 고속 산술 장치에서 올림수 예견가산기 스테이지의 수를 감소시키는 장치 및 방법
US6298368B1 (en) Method and apparatus for efficient calculation of an approximate square of a fixed-precision number
US4695970A (en) Linear predictive coding technique with interleaved sequence digital lattice filter
US5870322A (en) Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication
JP3660075B2 (ja) 除算装置
JPS63201825A (ja) 演算処理装置
JPH08314697A (ja) 符号付き／符号なし数兼用乗算器
JPS6226723B2 (enrdf_load_stackoverflow)
JPH0776914B2 (ja) 乗算回路
JPH03661B2 (enrdf_load_stackoverflow)
JPH01251133A (ja) 乗算回路及び方法
Al-Ibadi Hardware implementation for high-speed parallel adder for QSD 2D data arrays
JPS6259828B2 (enrdf_load_stackoverflow)
JPH06223097A (ja) 乗算器、積和演算器の回路記述の発生方法
JP2001249798A (ja) 規則的加算回路を使用して乗算器の性能を増大させる装置及び方法
JPH1011418A (ja) 積和演算装置
Vemula et al. ASIC Design of ALU with different multipliers

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees