JPS63197376A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a wide channel and to restrain hot carrier from generating, by forming, on the upper part of a MOS, a semiconductor layer exposing region and a region where the thickness of a surface insulating layer is gradually increased, and forming a P<-> region and N<-> region by ion implantation. CONSTITUTION:A gate electrode 4 is formed on a semiconductor substrate 1 via a gate oxide film 3, and a side-wall 5A composed of an insulative film is formed on both side-walls of the electrode 4. By applying these to a mask, P-type impurity ion is implanted, and a source.drain ion implantation region 6 is formed. After an insulative film 8 is formed on the surface of the substrate 1, a semiconductor layer 9A in which N-type impurity is doped and an insulative layer 10 are formed. After a resist 11 is flatly spread on the substrate 1, the layer 10 and the resist 11 are subjected to etching with the same speed till the surface of the layer 9A is exposed, and a semiconductor layer exposing region 14 and an insulative film thickness decrease region 15 are formed. The latter is a region in the periperal part of the former, and the thickness of the layer 10 is made gradually thin. After the resist is eliminated, P-type impurity ion is implanted, and a P<-> region 16 and an N<-> region 17 are formed in a region 14 and the layer 9A under the region 15, respectively.

Description

[Detailed description of the invention] [Summary] Joint Gate Complementary
In MOS FET, the lower part is P channel,
The upper part is N channel MO8, and the upper N channel M
To form O3, an exposed portion of the semiconductor surface and a region where the thickness of the insulating film gradually decreases are provided, and an N- region is formed by ion implantation to increase the effective channel length and suppress the generation of hot carriers, thereby improving the degree of integration.

[Industrial application field]

The present invention is a Joint Gate Complement.
The present invention relates to a method of manufacturing an MOS FET, and particularly to a method of manufacturing an N-channel MOS FET by placing an N-channel MOS on top and forming an N-jJl region to increase the effective channel length.

A C (Co
(plementary) MOS has the advantage of being able to construct low-power, high-speed operation logic circuits, but it is even better if the gates of both channel types are combined into a joint gate (abbreviated as JG) type. Since it can be configured compactly, the degree of integration can be increased.

In this JG type CM'O3, in which an N channel is formed on the substrate and a P channel is formed on the gate, if the N channel length is too narrow, many hot carriers (hot electrons) will be generated here, which is preferable in terms of characteristics. Therefore, there is a drawback that the gate width cannot be made too narrow and miniaturization is not possible.

In addition, in the reverse type, that is, the type in which a P channel is formed on the substrate and an N channel is formed on the gate, the MOS on the substrate side is a P channel, so hot carriers in this part become holes. Therefore, the occurrence is small,
Even if the channel length is narrowed, there is no problem with hot carriers.

However, in the N-channel MOS formed on the gate, the channel length is still too narrow, causing the generation of hot carriers (hot electrons), which is an obstacle to miniaturization.

In the present invention, a JG type C with a P channel on the substrate side.
MO3, and provides a manufacturing method that widens the effective length of the upper N channel.

[Conventional technology]

Figure 2 (a) to (f) show JG type C in conventional example (1).
This is a schematic cross-sectional view for explaining the manufacturing method of MO3, and is for a CMOS type in which an N channel is formed in the substrate and a P channel is formed above the gate electrode.

FIG. 2(a) shows a state in which a source/drain (hereinafter abbreviated as S/D) ion implantation N- region is formed after forming a gate electrode.

In this figure, reference numeral 1 denotes a P-type Si substrate, on which a 5i02 film 2, which is a field oxide film, is formed by the LOCO5 method using a nitride film as a mask. After removing the nitride film, a SiO film 3 serving as a gate oxide film is formed to a thickness of about 300 mm. Next, a polysilicon layer to become the gate electrode 4 is deposited, doped with phosphorus as an impurity, and then patterned.

The thickness of this polysilicon layer 4 is formed to be slightly higher than the height of the SiO□ film 2 by <3000 layers. That is, 5i (
When the h film 2 is formed to a thickness of 6000 mm, this SiO□
The film 2 is formed to a depth of about 300 to 0 from the surface of the Si substrate 1.

Next, using the gate electrode 4 as a mask, phosphorus (P") ions are implanted to form an S/D ion implantation N- region 21 in the surface layer of the Si substrate 1.

FIG. 2(b) shows a situation in which a Si0g film is deposited.

A SiO□ film 5 is deposited using the CVD method.

FIG. 2(c) shows a state in which an S/D ion implantation N'' region is formed after forming a 5in2 sidewall.

5iozzll! Anisotropic etching is performed on the gate electrode 4 to form sidewalls 5A of SiO□ on both side walls of the gate electrode 4. Next, arsenic (As') ions are implanted to form an S/D ion-implanted N'' region 22.
The ion implantation N+ region 22 is the S/D ion implantation N− region 2.
It is formed in a region that is set back from the sidewall 5A by the thickness of the sidewall 5A.

FIG. 2(d) shows a state in which an insulating film and a polysilicon layer are formed on the surface, this polysilicon layer is made into a single crystal, and then a BSG film is formed.

In this figure, a 5iOz insulating film is formed on the surface by thermal oxidation.
A film 8 is formed. Then, a polysilicon layer which is to become the semiconductor layer 9 is deposited thereon. This polysilicon layer 9 is doped with boron (B) to make it P-. Next, this polysilicon layer 9 is recrystallized by laser irradiation to form a single crystal layer 9A. Then, B S G (B
A film 23 of about 3,000 layers thick is formed.

In FIG. 2(e), the resist is applied and then etched back to expose the top of the single crystal layer.

The resist 24 is applied thickly to obtain a flat surface. Next, an etch bank is performed by anisotropic etching in which the etching speed of the BSG film and the resist are equal to expose the region above the gate electrode 4 of single crystal N9A. The anisotropic etching is performed by RIE (reactive ion etching) using CHh+CF4+02 as a gas.

In this etch-back, the BSG film 23 on the field oxide film 2 remains almost undamaged.

FIG. 2(f) shows a state in which a P'' region is formed in the single crystal layer by heat treatment after removing the remaining resist.

In this figure, the remaining resist 24A is removed. Then, heat treatment is performed to convert B (boron) in BSG into a single crystal layer 9.
A is diffused to form a P'' region 27. The region 9A in which boron is not diffused remains as a P- region, and this becomes a P channel, but boron is diffused not only vertically but also horizontally. Therefore, the p-sl region width is much narrower than the width of the exposed surface of the single crystal layer 9A.

In the JG type CMO3 formed in this way,
Shallow li adjacent to the S/DN"ji area of N-channel MO5
Although a tightly doped region, an N- region, is formed, hot carriers (hot electrons) in this region pose a problem, so the width of the gate electrode cannot be made very narrow, and miniaturization is therefore limited.

S/D ion implantation implantation area 21, S/D ion implantation N''
Ions in region 22 are activated by post-implantation heat treatment and are activated in S/DN− region 25 and S/DN″ region 2, respectively.
It becomes 6.

FIG. 3 is a schematic cross-sectional view of a JG type CMOS in conventional example (2).

What is shown in this figure is the conventional example (1) and (7) (
7) This is a type in which P and N are exchanged, and an N channel is formed on the substrate and a P channel is formed on the gate electrode, and is basically formed in the same process as conventional example (1). .

However, in the P-channel MO3, the generation of hot carriers is difficult, so there is no lightl in the St substrate 1.
A P- region, which is a y doped region, is not formed.

The P-channel MO3 on the gate electrode uses a P- single crystallized layer, and AsS G instead of the S/D N'' region BSG.
(Ar5entc 5ilicate Glass)
29 and diffuse arsenic (As) from it to form S/
Form the N' head area 28 of D. At this time, due to diffusion, N
- Since the region 28 is formed, there is considerable diffusion of As in the lateral direction, the channel length is narrowed, and hot carriers (electrons) are likely to be generated.

[Problem that the invention seeks to solve]

In JG type MOS FET, the lower part is P channel M
The structure of conventional example (2), which uses O3 and eliminates the possibility of hot carrier generation in the substrate, has an upper N-channel MO
3, the channel length becomes narrower than the exposed portion of the semiconductor surface, and hot carrier generation is not sufficiently suppressed.

The present invention aims to suppress the generation of real carriers by forming a channel wider than the exposed portion of the semiconductor surface.

[Means for solving problems]

The solution to the above problem involves forming a gate electrode on a semiconductor substrate via a gate oxide film, forming sidewalls made of an insulating film on both sides of the gate electrode, and masking the gate electrode and sidewalls. P-type impurity ions are implanted into the exposed surface area of the semiconductor substrate.
a step of forming a drain ion implantation region, a step of forming an insulating film on the surface of the semiconductor substrate, a step of forming a semiconductor layer doped with an N-type impurity, and further forming an insulating film layer on the semiconductor layer; After applying a resist to a flat surface on the semiconductor substrate, the insulating film layer and the resist are etched at the same speed until the surface of the semiconductor layer on the gate electrode is exposed. After the resist is removed, P-type impurity ions are implanted to form a P- region in the semiconductor layer exposed region, and the surrounding insulation layer is gradually thinned. This is achieved by the method of manufacturing a semiconductor device according to the present invention, which includes the step of forming an N- region in the semiconductor layer under the reduced film thickness region.

[Effect]

In JG type MO3FET, M formed on the lower substrate
By making the OS P-channel and avoiding the risk of hot carrier generation in the substrate, it is easier to miniaturize the structure, that is, increase the degree of integration, and the upper N-channel MO3 is formed above the gate electrode. In the insulating film on the surface of the N゛ conductor layer, an insulating film thickness reduction region where the thickness gradually decreases and a region where the surface of the N゛ conductor layer is exposed are provided, and P-type ions are implanted into this and a P- channel is formed by inversion. do.

Since the p-%fJ region is formed by ion implantation, not only the semiconductor layer exposed region but also the semiconductor layer under the thin film thickness region of the insulation film thickness reduction region is inverted, so that the region is wider than the semiconductor layer exposed region. can be made into a P-region. Furthermore, the N-half body layer near the region inverted to P-, N-
%l area.

Therefore, the effective channel length of the N-channel MO3 becomes large, and there is almost no possibility of hot carrier generation.

〔Example〕

Figures 1(a) to (i) show the JG type CMO8 in the present invention.
FIG. 3 is a schematic cross-sectional view for explaining the manufacturing method.

In these figures, objects that are the same as in FIG. 2 are designated by the same reference numerals.

FIG. 1(a) shows a state in which a gate electrode is formed on the gate oxide ridge.

In this figure, reference numeral 1 denotes an N-type St substrate, on which a SiO□ film 2, which is a field oxide film, is formed to a thickness of about 6000 by the LOCO3 method using a nitride film as a mask. After removing the nitride film, a Sing film 3 serving as a gate oxide film is formed to a thickness of about 300 mm. Next, a polysilicon layer which is to become the gate electrode 4 is deposited to a thickness of about 2,000 layers, doped with phosphorus as an impurity, and then patterned.

FIG. 1(b) shows the state in which the SiO□ film is deposited.

A 5 inch 2 film 5 is deposited to a thickness of about 2000 using the CVD method.

FIG. 1(c) shows a state in which the Sing sidewall is formed.

By performing anisotropic etching on the SiO2 film by approximately 3,000 people, Sing sidewalls 5A are formed on both side walls of the gate electrode 4. Anisotropic etching is gas:
C) lh”, pressure crab 0.2 Torr.

FIG. 1(d) shows a state in which an S/D ion implantation region P' is formed.

Using the gate electrode 4 and the sidewall 5A of 5in2 as a mask, boron (B+) ions are implanted into the Si substrate 1 at a dose of about IQ 1%/cmt, and S/
D ion implantation P'' region 6 is formed.

FIG. 1(e) shows a state in which an insulating film is formed.

By thermal oxidation, a Si film 8 serving as an insulating film is formed on the exposed silicon surface of the Si substrate 1 to a thickness of approximately 300 mm.

FIG. 1(f) shows a state in which a semiconductor layer is deposited and made into a single crystal.

A polysilicon layer 9 is formed to a thickness of about 3,000 layers using the CVD method. Next, the polysilicon layer 9 is recrystallized by laser irradiation to form a single crystal layer 9A as a semiconductor layer.
form. Next, add arsenic to this at about IQIS/cm"
Dope the single crystallized layer 9A to N'.

FIG. 1(g) shows a state in which, after the insulating film layer has been deposited, a resist with a flat surface is applied, and another resist pattern is further formed thereon.

Insulating film layer SiO□ film 10 film thickness 0 approx. 2000, CVD
Adhesion is formed using a method.

On top of this, a resist (photoresist, abbreviated as "Gashi-Sist") 11-1 is applied to a thickness of about 1.0 .mu.m, and the surface is finished flat. Next, after this resist 11-1 is cured, another resist 11-2 is applied thereon to a thickness of about 0.5 μm, and this resist 11-2 is patterned to form an opening 13. The size and position of the opening 13 may be such that the upper part of the swell of the 5iO1 film 10 centered on the gate electrode 4 is opened, and the upper part of the swell with the field oxide film 2 is covered.

FIG. 1(h) shows a state in which the top of the single crystallized layer has been exposed by etching back.

The resist 11 (resists 11-1 and 11-2 are collectively referred to as 11) and the Sing film 10 are anisotropically etched at a low etching rate to remove the single crystal layer 9A above the gate electrode 4. Etch until the top of the raised area is exposed. Thus, the area of the opening 13 can be etched evenly and a flat bottom surface can be formed.

Therefore, since the Sing film 10 is formed to be more inclined due to the layer 0 side wall 5A, it is thinner near the exposed area of the single crystallized layer 9A and the semiconductor layer exposed area 14, and becomes thicker (tapered) as it moves away. This is a region where the insulation film thickness is reduced.

CHF3+ CFA is used as an anisotropic etching gas.
Use +0□.

FIG. 1(i) shows a state in which B ions are implanted after removing the remaining resist.

The remaining resist 11A is removed. Then, B+ ions are implanted. At this time, the ions are implanted by adjusting the dose to such an extent that the exposed semiconductor layer region 14 of N' is inverted to the P- region 16 of P type.

The inversion region to P- extends not only to the semiconductor layer exposed region 14 but also to the semiconductor layer under the thin film thickness region of the insulating film thickness reduction region 15, so that it covers a wider area than the semiconductor layer exposed region 14. It can be a P-region. Further, the N゛ semiconductor layer near the region inverted to P- under the insulation film thickness reduction region 15 is converted to the N-131 region.

Thick Sing film 10 Single crystallized layer 9 under the layered region
A remains in the N+ territory.

The implanted ions in the S/D ion implantation P'' region 6 and the ions implanted into the single crystallized layer are activated by heat treatment after the ion implantation.

For example, the S/D ion implantation region 6 is the S/D region 18.
becomes.

In the JG type CMO3 formed in this way,
a P- region wider than the semiconductor layer exposed region in the N channel;
Since there is an N-9N region adjacent to it, there is no problem with hot carriers (hot electrons), and the gate electrode width can be narrowed to the extent that no problem occurs with the P channel, making it possible to miniaturize the gate electrode. .

〔Effect of the invention〕

In JG type CMO3, the lower part is P channel and the upper part is N channel.
To form the channel MO3 and the upper N-channel MO3, a semiconductor layer exposed region and a region where the thickness of the insulating film on the surface gradually increases are formed, and the N'' region is inverted by ion implantation to form a p-%7J region. and form the N-9M region,
Since the P-9M region is larger than the exposed semiconductor layer region and also has an N- region, there is almost no concern that hot electrons will be generated. Therefore, it becomes possible to proceed with miniaturization while ignoring the problem of hot electrons.

[Brief explanation of the drawing]

Figures 1(a) to (i) show the JG type CMO8 in the present invention.
FIG. 2(a) is a schematic cross-sectional diagram for explaining the manufacturing method of
-(f) are cross-sectional schematic diagrams for explaining the manufacturing method of the JG type CMOS 3 in conventional example (1). FIG. 3 is a cross-sectional schematic diagram of the JG type CMOS in conventional example (2). In these figures, ■ is a semiconductor substrate (Si substrate), 2 is a field oxide film (SiO□ film), 3 is a gate oxide film (SiO□ film), 4 is a gate electrode (polysilicon), 5 is a Sin film, 5A is a side wall, 6 is a g/D ion implantation P1 region, 8 is an insulating film (Si0g film), 9A is a semiconductor layer (single crystal layer), 10 is an insulating film layer (Sin, film), 11-1. 11-2 is a resist, 11A is a remaining resist, 13 is an opening, 14 is a semiconductor layer exposed region, 15 is an insulation film thickness reduction region, 16 is a P- region, 17 is an N- region, 18 is S/D region 1 Figure l Figure i Section 8 Figure 1 Figure 3 Speed 禾(,!IJ 2 Figure name: Snoring Shiruta?r)'s re-sealed surface 1,000 years ago] Figure 7

Claims (1)

[Claims] A gate electrode (4) is formed on a semiconductor substrate (1) via a gate oxide film (3), and side walls (5A) made of an insulating film are formed on both sides of the gate electrode (4). ), and implanting P-type impurity ions using the gate electrode (4) and sidewalls (5A) as masks, and forming the semiconductor substrate (1).
A source/drain ion implantation region (6
), and after forming an insulating film (8) on the surface of the semiconductor substrate (1),
A step of coating a semiconductor layer (9A) doped with an N-type impurity and an insulating film layer (10) on the semiconductor layer (9), and then coating a resist (11) on the semiconductor substrate (1). After applying it evenly, apply the semiconductor layer (9) on the gate electrode (4).
The insulating film layer (10) and the resist (11) are etched at the same rate until the surface of A) is exposed, and the thickness of the insulating film layer (9) is gradually increased in the semiconductor layer exposed region (18) and around it. After the step of forming a thinned insulating film thickness region (15) and removing the resist, P-type impurity ions are implanted to form a P^- region (16) in the exposed semiconductor layer region (14). A method for manufacturing a semiconductor device, comprising the step of forming an N^- region (17) in the semiconductor layer (9A) under the peripheral insulation film thickness reduced region (15).