JPS6319627A - Thin film transistor array - Google Patents

Abstract

PURPOSE:To prevent a line defect from being caused by making the resistance value between a scanning line and the gate electrode of a transition (TR) larger than the resistance values of the signal line and a signal line. CONSTITUTION:The resistance between the scanning line and the gate electrode of the TR is made larger than that of the scanning line and signal line. A gate 21a is made of a material different from the scanning line 4 and connected at a connection point A. Even if the gate and source of the TR short-circuit to each other, a voltage waveform which is applied originally between the signal line and scanning line does not vary regardless of the short-circuiting because the resistance of a short-circuit path is set larger than the resistance of signal lines Y1, Y2, and Y3, and scanning lines X1, X2, and X3 at the short- circuiting point. Therefore, a charging path to the electrode of a picture element 14 connecting with another normal TR on the scanning line or signal line is secured, a line defect which is an important defect on the scanning line or signal line is caused unlike before, and the defect is suppressed to the spot defect of the short-circuiting TR itself.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to thin film transistor arrays used in liquid crystal displays and the like.

2. Description of the Related Art Conventionally, a thin film transistor array used for this purpose generally has a structure as shown in FIG. 3, as shown in, for example, Japanese Unexamined Patent Publication No. 59-47623. That is, a thin film transistor (hereinafter referred to as TPT) 11 is provided whose gate electrodes are connected to the scanning lines x1 to XM and whose electrodes are connected to the signal lines Y1 to YM, and whose drain electrode is connected to the pixel electrode 26.
It is connected to the. A liquid crystal 13 is inserted between a picture element electrode and a counter ground electrode to display an independent picture element 1.
4. This element 14 acts isometrically as a capacitor, but in some cases an auxiliary capacitor may be added in parallel thereto.

The function of the TFT will be explained with reference to FIG. scanning line X,
, X2. X5... is a selection pulse P1.X5 as shown in FIG. P2. P3... are applied respectively.

When a specific scanning line, e.g. The voltage of the corresponding signal line is applied. When xl is switched to non-selection, the TPT becomes non-conductive, so the voltage applied to the picture element maintains the previous value until xl is selected in the next frame. In this way, a liquid crystal display using a TFT array is attracting attention because it can accurately and independently transmit the necessary signal voltage to each element 14, and therefore enables display with no crosstalk and a high contrast ratio. The cross-sectional structure of the transistor itself that functions in this manner is generally shown in FIG. 5, and when viewed from above, it is usually made as shown in FIG. 6.

Problems to be Solved by the Invention However, as the number of scanning lines and signal lines increases in such a configuration, it becomes extremely difficult to manufacture all TETs as good products. In particular, TPT has a gate 21, a source 22, and a drain 23, as shown in FIG. 5, an example of its cross-sectional structure.
7 because the layers are stacked with at least an insulating film 24 in between.
, there is a risk of shorting between the gate and source or between the gate and drain due to pinholes or other process problems. In particular, a short circuit between the gate and source of one TFT causes abnormal operation of all TPTs on the scanning line and signal line connected to the short circuit, resulting in a serious defect called a line defect.

The present invention has been made in view of the above problems, and provides a thin film transistor array having a structure in which line defects, which are serious defects, do not occur even if a certain transistor is defective. Means: In order to solve the above-mentioned problems, the thin film transistor array of the present invention has a structure in which the resistance of the scanning line and the gate electrode of the transistor is made high in both the scanning line and the signal line.

Operation The present invention has the above-described structure, and the gate and gate of the transistor.
Even if a short circuit occurs between sources, the resistance of the short circuit path is set to be higher than the resistance of the signal line and scanning line related to the short circuit point, so the voltage originally applied to the signal line and scanning line The waveform remains unchanged by short circuits.

Therefore, a charging path to the pixel electrodes connected to other normal transistors on these scanning lines or signal lines can be secured, and short circuits can be avoided without causing line defects, which are serious defects on the scanning lines or signal lines, as in the past. This can be limited to a point defect in the transistor itself.

EXAMPLE Hereinafter, a thin film transistor showing an example of the present invention will be explained from Kotobuki with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of a thin film transistor array in one embodiment of the present invention. In the figure, 1 is the scanning line
The resistance Rgs2 at the connection part connecting 1 to XM and the gate is the stray capacitance of the transistor, but in this case, the gate capacitance C
g Cool down. Other numbers are the same as in the conventional example shown in FIG.

FIG. 2(a) is a plan view of a thin film transistor according to the first embodiment 11FIJ of the present invention. The gate 21LL is made of a material different from that of the scanning line 4, and is connected to the gate 21LL by a connecting wire. Note that from the perspective of the present invention, the resistance between the scanning line and the gate is as thick as possible, the better; however, if it is too large, the product (time constant) of the gate capacitance of the transistor and the resistance between the scanning line and the gate
However, there is a risk that a situation may occur in which the gate voltage does not rise sufficiently during the time width of the selection pulse of the scanning line.

In order to avoid this, the resistance of the gate portion is set so that the above-mentioned time constant is smaller than the selection pulse width of the scanning line. That is, the capacitance of the transistor as seen from the gate is Cgs, the frame period is T1, and the number of scanning lines is M. The selection pulse width of the scanning line is T/M.

Assuming that the resistance of the gate portion is Rg, the following condition is required for the gate voltage to rise sufficiently: Cg-Rg<T/M. Now, as a relatively realistic value, M-5
00, T=16.7 m5ec, Cg=5
If pF is used, then Rg (6MQ is obtained.) If the resistance of the force scanning line is, for example, 10Ω, then in this example, the resistance of the gate section is determined by its shape and material so that 10Ω<Rg<<6MΩ. etc., you can choose.

FIG. 2(b) shows a second embodiment, in which the gate 21b of the transistor and the scanning line 4 are made of the same material and process, and the gate and scanning line are connected by a different high resistance film 28. .

In these examples, the scanning line is formed of 1000 to 2000 layers of Or, the semiconductor film 25 is amorphous silicon formed by plasma CVD, and the insulating film is also formed of plasma CVD.
Silicon nitride is formed by the VD method, and the signal lines, sources, and drains are made of muE. IT picture elements are transparent conductors
O is used. CrSi or the like can be used as the high resistance film of the gate connection portion.

FIG. 2(C) shows a third embodiment, in which the high resistance film 2
8 using n+α-8i. Since n+α-8i is a layer commonly used for ohmic contact between a semiconductor layer and a source/drain, this example
It has the advantage that the process is completely unchanged from the conventional method. The metal connection 29 uses the same material as the signal line source/drain. Further, the contact hole 3o is a hole made in the insulating film 24 to ensure contact between the scanning line or the gate electrode 21b and the metal connection 29.

The operation of the thin film transistor array configured as described above will be explained. First, the picture element electrode 26 receives information from the signal line 3 at the timing when the scanning line 4 is selected and is charged. Thereafter, the previous voltage is held until the same scanning line 4 is selected again in the next frame.

Next, if the gate and source of the transistor are short-circuited for some reason, conventionally the voltage waveform originally applied to the line defect on the scanning line 4 and signal line 3 connected to this transistor is not changed by the short-circuit. Therefore, line defects, which are serious defects on scanning lines or signal lines, as in the conventional case are not caused, and the short-circuited transistor itself can be limited to a point defect.

Effects of the Invention As described above, in the present invention, by providing a high resistance between the scanning line and the gate electrode, line defects, which are serious defects that occur in the prior art, can be reduced to point defects.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram of a thin film transistor array in one embodiment of the present invention, Fig. 2 (IL) is a planar structural diagram of a thin film transistor in the first embodiment, Fig. 2 (b),
(C) is a plan view of the structure of the thin film transistor in the second and third embodiments, FIG. 3 is an equivalent circuit diagram of a conventional thin film transistor array, and FIG. 4 is a waveform diagram of the selection pulse applied to the scanning line of the thin film transistor array. , FIG. 5 is a sectional view of a conventional thin film transistor, and FIG. 6 is a plan view of the same structure. 1... Connection resistance, 2... Gate capacitance, 11... TFT, 13... Liquid crystal,
14...Picture element, xl. X2. X,...scanning line, Yl, Y2. Y
3...Signal line 0 Name of agent Patent attorney Toshio Nakao and 1 other person/-
--Gi Ukeyo 屹t SA's degree ℃ measure 2---Date graduation I 艷O) /l-11-cho FT 1 figure 16-Kan et al./4-11 Ori Takashi Xt Cold X3- 11 foot fish honey YIY2no --- Traffic light Figure 2 Figure 2 (C,) Bubbles 3 naked //--- TFT / 3-11 liquid easy / 4-11 roaring Y1 γz Y5 --- Ichiyuro Neighborhood Figure 4 Figure 5 Figure 27 Cut off 14 forks Figure 6

Claims (3)

[Claims] (1) A plurality of scanning lines, a plurality of signal lines, a transistor controlled by the scanning line corresponding to the intersection point of each scanning line and each signal line, and a picture element electrode corresponding to the transistor; A thin film transistor array, characterized in that a resistance value between the scanning line and the gate electrode of the transistor is greater than resistance values of the scanning line and the signal line. (2) The resistance value between the scanning line and the gate electrode of the transistor is set so that the product of the resistance value and the gate capacitance of the transistor is shorter than the pulse width applied to the scanning line. The thin film transistor array described in (1). (3) The gate is made of the same material with the same sheet resistance as the scanning line, and the resistance of the tangent between the gate and the scanning line is made of a material with higher resistance than the scanning line and the gate material. A thin film transistor array according to claim (1) or (2).