JPS63194773U - - Google Patents

Info

Publication number
JPS63194773U
JPS63194773U JP1987086951U JP8695187U JPS63194773U JP S63194773 U JPS63194773 U JP S63194773U JP 1987086951 U JP1987086951 U JP 1987086951U JP 8695187 U JP8695187 U JP 8695187U JP S63194773 U JPS63194773 U JP S63194773U
Authority
JP
Japan
Prior art keywords
module
electrode pattern
chips
side direction
pattern separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987086951U
Other languages
English (en)
Japanese (ja)
Other versions
JPH081109Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987086951U priority Critical patent/JPH081109Y2/ja
Publication of JPS63194773U publication Critical patent/JPS63194773U/ja
Application granted granted Critical
Publication of JPH081109Y2 publication Critical patent/JPH081109Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Credit Cards Or The Like (AREA)
JP1987086951U 1987-06-04 1987-06-04 複数チップ内蔵のｉｃモジュール Expired - Lifetime JPH081109Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987086951U JPH081109Y2 (ja) 1987-06-04 1987-06-04 複数チップ内蔵のｉｃモジュール

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987086951U JPH081109Y2 (ja) 1987-06-04 1987-06-04 複数チップ内蔵のｉｃモジュール

Publications (2)

Publication Number Publication Date
JPS63194773U true JPS63194773U (ar) 1988-12-15
JPH081109Y2 JPH081109Y2 (ja) 1996-01-17

Family

ID=30943727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987086951U Expired - Lifetime JPH081109Y2 (ja) 1987-06-04 1987-06-04 複数チップ内蔵のｉｃモジュール

Country Status (1)

Country Link
JP (1) JPH081109Y2 (ar)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166566U (ar) * 1988-05-17 1989-11-22
JP2005183925A (ja) * 2003-11-28 2005-07-07 Sumitomo Bakelite Co Ltd 半導体装置及びその製造方法
JP2005293460A (ja) * 2004-04-05 2005-10-20 Matsushita Electric Ind Co Ltd 非接触ｉｃカード用インレットおよび非接触ｉｃカード

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177872U (ar) * 1985-04-24 1986-11-06
JPS62271493A (ja) * 1986-05-20 1987-11-25 日立マクセル株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177872U (ar) * 1985-04-24 1986-11-06
JPS62271493A (ja) * 1986-05-20 1987-11-25 日立マクセル株式会社 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166566U (ar) * 1988-05-17 1989-11-22
JP2005183925A (ja) * 2003-11-28 2005-07-07 Sumitomo Bakelite Co Ltd 半導体装置及びその製造方法
JP4681260B2 (ja) * 2003-11-28 2011-05-11 住友ベークライト株式会社 半導体装置及びその製造方法
JP2005293460A (ja) * 2004-04-05 2005-10-20 Matsushita Electric Ind Co Ltd 非接触ｉｃカード用インレットおよび非接触ｉｃカード

Also Published As

Publication number Publication date
JPH081109Y2 (ja) 1996-01-17

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