JPS63193554A - Gaas semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the size of the element of an integrated circuit, by using part of wirings as a bypass capacitor, thereby omitting another space for forming the bypass capacitor. CONSTITUTION:A dielectric layer is formed between double-layer wiring layers, which comprise a DC power source wiring 1 and a DC wiring power source wiring 2 that is provided so as to overlap with the DC power source wiring 1. In this way, the overlapped parts of both wirings become a parallel plate type bypass capacitor 6, with the DC power source wirings 1 and 2 being both electrodes. Furthermore, three DC power-source wiring layers are provided, and dielectric layers are formed between the wiring layers. Thus bypass capacitors can be formed at the overlapped parts of the wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a GaAs semiconductor integrated circuit, and particularly to a GaAs semiconductor integrated circuit that requires a bypass capacitor.

[Conventional technology]

Conventionally, when this type of GaAs semiconductor integrated circuit requires a bypass capacitor, as shown in FIG. A bypass capacitor 8 of a parallel plate type using a space is formed and used, or a Schottky barrier diode is used as a capacitor by applying a reverse bias.

[Problem that the invention seeks to solve]

The conventional GaAs semiconductor integrated circuit described above requires its own space for forming a bypass capacitor. If so, 1
There is a drawback that a space of 4000 μm 2 is required, which increases the chip size of the integrated circuit.

In addition, in the case of a capacitor using a Schottky barrier diode, it depends on the concentration of the active layer, but in the case of the normally used concentration (2X 10'7/crs3), it is about 1600
Although it requires a space of μm2, which is less than 1/8 of the space required for a bypass capacitor, it has the disadvantage that the applied voltage is limited by the reverse withstand voltage.

[Means for solving problems]

In the GaAs semiconductor integrated circuit of the present invention, at least two layers of DC power supply wiring are stacked with a dielectric material interposed between the layers, and the overlapping regions of the two opposing DC power supply wirings are used as respective electrodes. Forms a flat plate bypass capacitor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a first embodiment of the invention.

As shown in FIG. 1, a dielectric layer is formed between two layers of wiring consisting of a DC power supply wiring 1 and a DC power supply wiring 2 provided so that a portion thereof overlaps with the DC power supply wiring 1. .

With this configuration, the overlapping portion of both wirings becomes a parallel plate type bypass capacitor 6 in which the DC power supply wirings 1 and 2 serve as both electrodes.

FIG. 2 is a plan view of a second embodiment of the invention.

As shown in FIG. 2, in the second embodiment, a DC power supply wiring 3 is further added to the first embodiment described above to form three layers, with a dielectric layer formed between each wiring layer, and the DC power supply wiring 1 and Bypass capacitors 6 and 7 are formed at the overlapping portions of DC power supply wirings 2 and 3, respectively.

〔Effect of the invention〕

As explained above, in the GaAs semiconductor integrated circuit of the present invention, by using a part of the wiring as a bypass capacitor, there is no need to intentionally secure a separate space for forming the bypass capacitor. This has the effect of reducing the element size.

[Brief explanation of the drawing]

1 and 2 are plan views of first and second embodiments of the present invention, respectively, and FIG. 3 is a plan view of an example of a conventional GaAs semiconductor integrated circuit. 1-5...DC power supply wiring, 6-8...Bypass capacitor. Half I Kunime 2 Concave

Claims (1)

[Claims] A parallel plate type bypass capacitor is formed by stacking at least two layers of DC power wiring with a dielectric interposed between the layers, and using the overlapping regions of the two opposing DC power wiring as respective electrodes. GaAs semiconductor integrated circuit.